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| PRELIMINARY Am79C901A HomePHYTM Single-Chip 1/10 Mbps Home Networking PHY DISTINCTIVE CHARACTERISTICS n Fully integrated 1 Mbps HomePNA Physical Layer (PHY) as defined by Home Phoneline Networking Alliance (HomePNA) specification 1.1 -- Optimized for home networking applications over existing telephone wire -- Media Independent Interface (MII)-compatible for connecting external Media Access Controller (MAC) -- In-band control features: Adjustable power and speed levels 32 bits of reserved in-band messaging piggybacked on Ethernet packet -- Register programmable features: Power control Speed control Performance registers Optional control of Squelch algorithm Major frame timing parameters programmable: ISBI, AID ISBI, pulse width, inter-symbol time -- any1HomeTM link detection: Indicates to the MAC that a valid home networking node has been detected Detects a network failure and allows the upper layer protocol to take corrective action n Fully integrated 10 Mbps Ethernet transceiver -- Comprehensive Auto-Negotiation implementation -- IEEE 802.3u-compliant MII -- Full-duplex operation supported on the MII port with independent Transmit (TX) and Receive (RX) channels -- Optimized for 10BASE-T applications n Compliant with HomePNA specification 1.1 n General Purpose Serial Interface (GPSI)/Serial Peripheral Interface (SPI) n Extensive programmable internal/external loopback capabilities n Extensive LED status support n IEEE 1149.1-compliant JTAG Boundary Scan test access port interface n Very low power consumption n +3.3 V power supply along with 5 V tolerant I/Os enable broad system compatibility -- XTAL1 supports 3.3 V I/O only -- XTAL2 supports 1.0 V I/O only n Available in 68-pin PLCC and 80-pin TQFP packages n Industrial Temperature Support (-40C to +85C) GENERAL DESCRIPTION The Am79C901A HomePHY is a single-chip device that contains both a physical layer (PHY) for 1 Mbps data networking over existing residential telephone wiring based on the specification published by HomePNA and a physical layer for supporting the IEEE 802.3 standard for 10BASE-T. The HomePHY is targeted at embedded applications and has both GPSI and MII-compatible interfaces. The integrated HomePNA transceiver is a physical layer device that enables data networking at speeds up to 1 Mbps over existing residential phone wiring regardless of topology and without disrupting telephone (POTS) service. The integrated Ethernet transceiver is a physical layer device supporting the IEEE 802.3 standard for 10BASE-T. It provides all of the PHY layer functions required to support 10 Mbps data transfer speeds. A compliant IEEE 1149.1 JTAG test interface for board level testing is provided. The Am79C901A PHY also provides on-chip LED drivers for collision, link integrity, speed, activity, and power output. The Am79C901A PHY is fabricated in an advanced low power 3.3 V CMOS process to provide low operating current for power sensitive applications. T he A m79C901A P H Y is avai lable in the commercial temperature range (0C to +70C) in 68-pin PLCC and 80-pin TQFP packages. The Am79C901A also suppor ts the industrial temperature range (-40C to +85C) in the 80-pin TQFP package. The industrial temperature range is well suited to environments with enclosures with restricted air flow or outdoor equipment. Publication# 22304 Rev: C Amendment/0 Issue Date: July 2000 Refer to AMD's Website (www.amd.com) for the latest information. PRELIMINARY BLOCK DIAGRAM SPEED POWER COL ACT LINK TDO TDI TCLK TMS 1Mbps HomePNA PHY LED Interface JTAG Port Control Link Control PHY_SEL PHY_AD ISOLATE MII/GPSI GM_MODE RXDAT, RXCLK, RXCRS, CLS, TXDAT, TXCLK, TXEN or RXD[3:0], TXD[3:0], CRS, COL, RX_DV, TX_EN, TX_CLK, RX_CLK, RX_ER MDC, MDIO or SCLK, SDI, SDO, CS Transmit State Machine Drive Control HRTXRXP/N Data Interface Receive State Machine Analog Front End DATA MII/GPSI Interface DATA PHY Control & Registers 10BASE-T PHY CONTROL CONTROL Link Control Transmit State Machine TX Data Interface Receive State Machine RX CONTROL Clock Reference PHY Control & Registers XTAL1 XTAL2 XCLK/XTAL 22304B-1 2 Am79C901A PRELIMINARY TABLE OF CONTENTS AM79C901A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CONNECTION DIAGRAM (PL 068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CONNECTION DIAGRAM (PQT 80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN DESIGNATIONS (PL 068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PIN DESIGNATIONS (PQT 80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PIN DESIGNATIONS (PL 068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PIN DESIGNATIONS (PQT 80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Listed By Driver Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 GPSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI Interface (Slave Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IEEE 1149.1 (JTAG) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ethernet Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 HomePNA PHY Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PHY Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 S_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 GPSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial Peripheral Interface (SPI-Slave) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MII-Compatible Interface for HomePNA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MII-Compliant Interface for 10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1 Mbps HomePNA PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 HomePNA PHY Medium Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 HomePNA PHY Symbol Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Time Interval Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 JAM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Access ID Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Silence Interval (AID symbol 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Mode Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1 Mbps HomePNA PHY Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 any1Home Link Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Twisted Pair Interface Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Am79C901A 3 PRELIMINARY Reverse Polarity Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 (JTAG) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAP Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Register and Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Mbps HomePNA PHY Management Registers (HPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR0: HomePNA PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR1: HomePNA PHY Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR2 and HPR3: HomePNA PHY ID Registers (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR4: HomePNA PHY Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register (Register 5). . . . . . . . . . . . . . . . . HPR6: HomePNA PHY Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . . . . . . . . . HPR7: HomePNA PHY Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers: HPR8 - HPR15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR16: HomePNA PHY Control Register (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR17: HomePNA PHY Status/Control Register (Register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR18 and HPR19: HomePNA PHY TxCOMM Registers (Registers 18 and 19) . . . . . . . . . . . . . . . . . . HPR20 and HPR21: HomePNA PHY RxCOMM Registers (Registers 20 and 21) . . . . . . . . . . . . . . . . . . HPR22: HomePNA PHY AID Register (Register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR23: HomePNA PHY Noise Control Register (Register 23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR24: HomePNA PHY Noise Control 2 Register (Register 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR25: HomePNA PHY Noise Statistics Register (Register 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR26: HomePNA PHY Event Status Register (Register 26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR27: HomePNA PHY AID Control Register (Register 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR28: HomePNA PHY ISBI Control Register (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR29: HomePNA PHY TX Control Register (Register 29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR30: HomePNA PHY Drive Level Control Register (Register 30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPR31: HomePNA PHY Analog Control Register (Register 31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T PHY Management Registers (TBRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBR0: 10BASE-T PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBR1: 10BASE-T Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBR2 and TBR3: 10BASE-T PHY Identifier Register (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . . . . TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . . . . . . . . . . . TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers (Registers 8-15, 18, 20-23, and 25-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBR16: 10BASE-T Status and Enable Register (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBR17: 10BASE-T PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBR19: 10BASE-T PHY Management Extension Register (Register 19) . . . . . . . . . . . . . . . . . . . . . . . . TBR24: 10BASE-T Summary Status Register (Register 24). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Transmit Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Receive Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Transmit Clock Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Receive Clock Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Mbps HomePNA Transmit Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 40 40 40 40 40 40 40 41 41 41 41 43 43 44 45 46 47 48 49 49 49 50 51 51 52 52 52 53 53 54 54 55 55 55 56 56 57 58 59 60 61 62 62 62 63 64 65 65 66 66 67 68 68 68 69 69 69 70 71 71 72 4 Am79C901A PRELIMINARY 1 Mbps HomePNA Receive Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Mbps HomePNA Clock Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Transmit Timing (MII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Receive Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Transmit Clock Timing (MII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Receive Clock Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Mbps HomePNA Transmit Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Mbps HomePNA Receive Timing (MII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Mbps HomePNA Clock Timing (MII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDC/MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T PMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Mbps HomePNA Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clock (XTAL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHYSICAL DIMENSIONS*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PL 068 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQT 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 74 75 75 76 78 78 79 80 81 82 83 84 85 86 87 87 88 88 89 Am79C901A 5 PRELIMINARY LIST OF FIGURES Figure 1. Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 2. RXPKT - RXCRS Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 3. RXPKT - RXCRS Cleared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 4. TXPKT - TXEN Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 5. TXPKT - RXCLK Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 6. TXPKT - TXEN Cleared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7. TXPKT - CLS Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 8. RXPKT - CLS Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 9. Operation of the SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 10. SPI Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 11. Aborted Operation of the SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 12. First Operation Following an Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 13. Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. MII Start of Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 15. MII End of Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 16. HomePNA PHY Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 17. AID Symbol Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Figure 18. AID Symbol Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Figure 19. Transmit Data Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 20. Receive Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 21. RLL 25 Coding Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Figure 22. 10BASE-T Transmit and Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Figure 23. Normal and Tri-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Figure 24. 10 Mbps Transmit Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Figure 25. 10 Mbps Receive Start of Packet Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Figure 26. 10 Mbps Receive End of Packet Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 27. 10 Mbps Transmit and Receive Clock Timing (GPSI). . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 28. 1 Mbps HomePNA Transmit Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 29. 1 Mbps HomePNA Receive Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Figure 30. 1 Mbps HomePNA Clock Timing (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Figure 31. 10 Mbps Transmit Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Figure 32. 10 Mbps Receive Start of Packet Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Figure 33. 10 Mbps Receive End of Packet Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Figure 34. 10 Mbps Transmit and Receive Clock Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Figure 35. 1 Mbps HomePNA Transmit Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Figure 36. 1 Mbps HomePNA Receive Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Figure 37. 1 Mbps HomePNA Clock Timing (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Figure 38. MII Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Figure 39. SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Figure 40. 10 Mbps Transmit (TX) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Figure 41. 10 Mbps Receive (RX) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Figure 42. HomePNA PHY AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Figure 43. JTAG (IEEE 1149.1) Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Figure 44. External Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6 Am79C901A PRELIMINARY LIST OF TABLES Table 1. Clock Source Selection 21 Table 2. GPSI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 3. SPI Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 4. MII-Compatible Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 5. MII Control Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 6. HomePNA PHY Pulse Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Table 7. Access ID Symbol Pulse Positions and Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 8. Blanking Interval Speed Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 9. Master Station Control Word Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 10. Auto-Negotiation Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 11. LED Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 12. IEEE 1149.1 Supported Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 13. BSR Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 14. Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 15. Boundary Scan Ring Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 16. 1 Mbps HomePNA PHY Management Registers (HPRs) . . . . . . . . . . . . . . . . . . . . . . .43 Table 17. HPR0: HomePNA PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 18. HPR1: HomePNA PHY Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 19. HPR2: HomePNA PHY ID Register (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 20. HPR3: HomePNA PHY ID Register (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 21. HPR4: HomePNA PHY Auto-Negotiation Advertisement Register (Register 4) . . . . . .47 Table 22. HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register Base Page Format (Register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 23. HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register Next Page Format (Register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 24. HPR6: HomePNA PHY Auto-Negotiation Expansion Register (Register 6) . . . . . . . . .49 Table 25. HPR7: HomePNA PHY Auto-Negotiation Next Page Register (Register 7) . . . . . . . . .49 Table 26. HPR16: HomePNA PHY Control Register (Register 16) . . . . . . . . . . . . . . . . . . . . . . . .50 Table 27. HPR17: HomePNA PHY Status/Control Register (Register 17) . . . . . . . . . . . . . . . . . .51 Table 28. HPR18 and HPR19: HomePNA PHY TxCOMM Registers (Registers 18 and 19) . . . .52 Table 29. HPR20 and HPR21: HomePNA PHY RxCOMM Registers (Registers 20 and 21) . . . .52 Table 30. HPR22: HomePNA PHY AID Register (Register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 31. HPR23: HomePNA PHY Noise Control Register (Register 23) . . . . . . . . . . . . . . . . . . 53 Table 32. HPR24: HomePNA PHY Noise Control 2 Register (Register 24) . . . . . . . . . . . . . . . . .53 Table 33. HPR25: HomePNA PHY Noise Statistics Register (Register 25) . . . . . . . . . . . . . . . . .54 Table 34. HPR26: HomePNA PHY Event Status Register (Register 26) . . . . . . . . . . . . . . . . . . .54 Table 35. HPR27: HomePNA PHY AID Control Register (Register 27) . . . . . . . . . . . . . . . . . . . .55 Table 36. HPR28: HomePNA PHY ISBI Control Register (Register 28) . . . . . . . . . . . . . . . . . . . 55 Table 37. HPR29: HomePNA PHY TX Control Register (Register 29) . . . . . . . . . . . . . . . . . . . . .55 Table 38. HPR30: HomePNA PHY Drive Level Control Register (Register 30) . . . . . . . . . . . . . .56 Table 39. HPR31: HomePNA PHY Analog Control Register (Register 31) . . . . . . . . . . . . . . . . .56 Table 40. 10BASE-T PHY Management Registers (TBRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 41. TBR0: 10BASE-T PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 42. TBR1: 10BASE-T PHY Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 43. TBR2: 10BASE-T PHY Identifier Register (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . .60 Table 44. TBR3: 10BASE-T PHY Identifier Register (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . .60 Table 45. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . 61 Table 46. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) Base Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Table 47. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) Next Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Table 48. TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . .63 Table 49. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . .63 Table 50. TBR16: 10BASE-T Status and Enable Register (Register 16). . . . . . . . . . . . . . . . . . . 64 Table 51. TBR17: 10BASE-T PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . 65 Table 52. TBR19: 10BASE-T PHY Management Extension Register (Register 19) . . . . . . . . . . .66 Table 53. TBR24: 10BASE-T Summary Status Register (Register 24) . . . . . . . . . . . . . . . . . . . .66 Am79C901A 7 PRELIMINARY CONNECTION DIAGRAM (PL 068) LED_ACTIVITY LED_POWER LED_SPEED MDC/SCLK MDIO/SDO LED_LINK LED_COL ISOLATE MII/GPSI PHY_AD 9 RXD1 RXD0/RXDAT DVSS RX_DV DVDD RX_CLK/RXCLK AVDD PHY_SEL DVDD RX_ER DVSS GM_MODE TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT TXD1/SDI NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 NC RXAVDD RX+ AVSS TXAVDD TX+ AVSS IREF AVDD HRTXRXP AVDD HRTXRXN AVSS AVSS AVDD Am79C901A HomePHY RESET 52 51 50 49 48 47 46 45 44 NC DVDD DVSS DVSS RXD2 RXD3 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 XCLK/XTAL XTAL2 XTAL1 CRS/RXCRS DVDD DVDD TXD3/CS COL/CLS AVDD TMS TDO DVSS DVSS TXD2 TCK TDI TEN Note: NC pins are reserved and should be left unconnected. 22304B-2 8 Am79C901A PRELIMINARY CONNECTION DIAGRAM (PQT 80) LED_ACTIVITY LED_POWER LED_SPEED MDC/SCLK MDIO/SDO LED_LINK LED_COL MH/GPSI ISOLATE PHY_AD RESET DVDD RXD2 79 RXD3 DVSS DVSS TEN NC 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 NC NC 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC NC RX01 RXD0/RXOAT DVSS RX_DV DVDD RX_CLK/RXCLK AVDD PHY_SEL DVDD RX_ER DVSS GM_MODE TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT TXD1/SDI NC NC NC NC RXAVDD RX+ AVSS TXAVDD TX+ AVSS IREF AVDD HRTXRXP AVDD HRTXRXN AVSS AVSS AVDD NC NC Am79C901A HomePHY 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AVDD 39 NC CRS/RXCRS TXD2 XCLK/XTAL NC NC TXD3/CS DVSS COL/CLS DVSS DVDD DVDD TDK TMS XTAL2 XTAL1 TDO Note: NC pins are reserved and should be left unconnected. TDI NC 40 22304B- Am79C901A 9 PRELIMINARY PIN DESIGNATIONS (PL 068) Listed By Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Name LED_LINK LED_COL LED_ACTIVITY DVDD LED_POWER LED_SPEED DVSS RXD3 RXD2 RXD1 RXD0/RXDAT DVSS RX_DV DVDD RX_CLK/RXCLK AVDD PHY_SEL Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 DVDD RX_ER DVSS GM_MODE TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT TXD1/SDI NC TXD2 TXD3/CS DVSS COL/CLS DVSS CRS/RXCRS DVDD DVDD Pin Name Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 TDO TCK TMS TDI XCLK/XTAL XTAL2 XTAL1 AVDD NC AVDD AVSS AVSS HRTXRXN AVDD HRTXRXP AVDD IREF Pin Name Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 AVSS TX+ AVDD TXAVSS RX+ AVDD RXNC RESET TEN MII/GPSI PHY_AD ISOLATE MDIO/SDO DVSS MDC/SCLK Pin Name Note: NC pins are reserved and should be left unconnected. 10 Am79C901A PRELIMINARY PIN DESIGNATIONS (PQT 80) Listed By Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC NC RXD1 RXD0/RXDAT DVSS RX_DV DVDD RX_CLK/RXCLK AVDD PHY_SEL DVDD RX_ER DVSS GM_MODE TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT TXD1/SDI NC NC Pin Name Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC NC TXD2 TXD3/CS DVSS COL/CLS DVSS CRS/RXCRS DVDD DVDD TDO TCK TMS TDI XCLK/XTAL XTAL2 XTAL1 AVDD NC NC Pin Name Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 NC NC AVDD AVSS AVSS HRTXRXN AVDD HRTXRXP AVDD IREF AVSS TX+ AVDD TXAVSS RX+ AVDD RXNC NC Pin Name Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 NC NC RESET TEN MII/GPSI PHY_AD ISOLATE MDIO/SDO DVSS MDC/SCLK LED_LINK LED_COL LED_ACTIVITY DVDD LED_POWER LED_SPEED DVSS RXD3 RXD2 NC Pin Name Note: NC pins are reserved and should be left unconnected. Am79C901A 11 PRELIMINARY PIN DESIGNATIONS (PL 068) Listed By Group Pin Name Configuration MII/GPSI GM_MODE ISOLATE PHY_SEL PHY_AD Board Interface RESET XCLK/XTAL XTAL1 XTAL2 IREF LED_COL LED_ACTIVITY LED_LINK LED_SPEED LED_POWER RESET Oscillator/Crystal Select Crystal Input (20 MHz XTAL/60 MHz CLK) Crystal Output (20 MHz XTAL) Tied to GND via a 12.1 k 1% resistor Collision Indication Activity Indication Link Valid Indication High Speed Indication High Power Indication I I I O I O O O O O - - - XTAL - LED LED LED LED LED 1 1 1 1 1 1 1 1 1 1 Selects MII or GPSI mode Selects MDC/MDIO and GPSI data Isolates device if register isolate bit is set = 1 Defines default PHY Defines bit 2 of the PHY address I I I I I - - - - - 1 1 1 1 1 Pin Function Type Driver Type Number of Pins 1 Mbps HomePNA PHY Network Ports HRTXRXP/N Receive/Transmit Data I/O - 2 10BASE-T PHY Network Ports TX RX MII Interface TX_CLK TXD[3:0] TX_EN RX_CLK RXD[3:0] RX_ER RX_DV MDC MDIO CRS COL MII Transmit Clock MII Transmit Data MII Transmit Enable MII Receive Clock MII Receive Data MII Receive Error MII Receive Data Valid MII Management Data Clock MII Management Data Input/Output Carrier Sense Collision O I I O O O O I I/O O O OMII - - OMII OMII OMII OMII - TSMII OMII OMII 1 4 1 1 4 1 1 1 1 1 1 Serial Transmit Data Serial Receive Data O I - - 2 2 12 Am79C901A PRELIMINARY Number of Pins Pin Name GPSI Interface TXCLK TXDAT TXEN RXCLK RXDAT RXCRS CLS SPI Interface SCLK SDI SDO CS SPI Clock SPI Data In SPI Data Out Chip Select Pin Function Type Driver Type GPSI Transmit Clock GPSI Transmit Data GPSI Transmit Enable GPSI Receive Clock GPSI Receive Data Carrier Sense Collision O I I O O O O OMII - - OMII OMII OMII OMII 1 1 1 1 1 1 1 I I O I - - TSMII - 1 1 1 1 IEEE 1149.1 (JTAG) Test Access Port Interface TCK TMS TDI TDO Power Supply DVDD AVDD DVSS AVSS Test Interface TEN Test Enable I - 1 Digital Power Analog Power Digital Ground Analog Ground P P G G - - - - 6 6 7 3 Test Clock Test Mode Select Test Data In Test Data Out I I I O - - - TS 1 1 1 1 Am79C901A 13 PRELIMINARY PIN DESIGNATIONS (PQT 80) Listed By Group Pin Name Configuration MII/GPSI GM_MODE ISOLATE PHY_SEL PHY_AD Board Interface RESET XCLK/XTAL XTAL1 XTAL2 IREF LED_COL LED_ACTIVITY LED_LINK LED_SPEED LED_POWER RESET Oscillator/Crystal Select Crystal Input (20 MHz XTAL/60 MHz CLK) Crystal Output (20 MHz XTAL) Tied to GND via a 12.1 k 1% resistor Collision Indication Activity Indication Link Valid Indication High Speed Indication High Power Indication I I I O I O O O O O - - - XTAL - LED LED LED LED LED 1 1 1 1 1 1 1 1 1 1 Selects MII or GPSI mode Selects MDC/MDIO and GPSI data Isolates device if register isolate bit is set = 1 Defines default PHY Defines bit 2 of the PHY address I I I I I - - - - - 1 1 1 1 1 Pin Function Type Driver Type Number of Pins 1 Mbps HomePNA PHY Network Ports HRTXRXP/N Receive/Transmit Data I/O - 2 10BASE-T PHY Network Ports TX RX MII Interface TX_CLK TXD[3:0] TX_EN RX_CLK RXD[3:0] RX_ER RX_DV MDC MDIO CRS COL MII Transmit Clock MII Transmit Data MII Transmit Enable MII Receive Clock MII Receive Data MII Receive Error MII Receive Data Valid MII Management Data Clock MII Management Data Input/Output Carrier Sense Collision O I I O O O O I I/O O O OMII - - OMII OMII OMII OMII - TSMII OMII OMII 1 4 1 1 4 1 1 1 1 1 1 Serial Transmit Data Serial Receive Data O I - - 2 2 14 Am79C901A PRELIMINARY Number of Pins Pin Name GPSI Interface TXCLK TXDAT TXEN RXCLK RXDAT RXCRS CLS SPI Interface SCLK SDI SDO CS SPI Clock SPI Data In SPI Data Out Chip Select Pin Function Type Driver Type GPSI Transmit Clock GPSI Transmit Data GPSI Transmit Enable GPSI Receive Clock GPSI Receive Data Carrier Sense Collision O I I O O O O OMII - - OMII OMII OMII OMII 1 1 1 1 1 1 1 I I O I - - TSMII - 1 1 1 1 IEEE 1149.1 (JTAG) Test Access Port Interface TCK TMS TDI TDO Power Supply DVDD AVDD DVSS AVSS Test Interface TEN Test Enable I - 1 Digital Power Analog Power Digital Ground Analog Ground P P G G - - - - 6 6 7 3 Test Clock Test Mode Select Test Data In Test Data Out I I I O - - - TS 1 1 1 1 Am79C901A 15 PRELIMINARY PIN DESIGNATIONS Listed By Driver Type The following table describes the various types of output drivers used in the Am79C901A PHY. All IOL and IOH values shown in the table apply to 3.3 V signaling. A sustained tri-state signal is an active-low signal that is driven high for one clock period before it is left floating. TX is a differential output driver. Its characteristics and those of the XTAL2 output are described in the DC Characteristics section. Driver Name LED TS OMII TSMII Type LED Tri-State Tri-State Tri-State IOL (mA) 12 6 4 4 IOH (mA) 0.4 2 4 4 Load (pF) 50 50 50 150 Note: For reference only. See DC specification for actual limits. 16 Am79C901A PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C901A J\V C\I \T ALTERNATE PACKAGING OPTION \T = Tape and Reel TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE J = Plastic Leaded Chip Carrier (PL 068) V = Thin Plastic Quad Flat Pack (PQT 80) SPEED OPTION Not applicable DEVICE NUMBER/DESCRIPTION Am79C901A HomePHY Single-Chip 1/10 Mbps Home Networking PHY Valid Combinations Am79C901A JC, JC\T VC, VI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C901A 17 PRELIMINARY PIN DESCRIPTIONS Configuration Pins MII/GPSI MII/GPSI Input MII/GPSI selects between the MII and the GPSI interface. This pin must be connected to either VDD or VSS. Changing the state of this pin is prohibited. the MII or the SPI command and control interface (external control mode), this pin selects which PHY data and status signals will be driven onto the interface. When set to a LOW, the HomePNA PHY data and status signals will be driven onto the interface. When set to a HIGH, the 10BASE-T PHY data and status signals will be driven onto the interface. This pin functions in conjunction with the ISOLATE pin. LOW = 1 Mbps HomePNA PHY HIGH = 10BASE-T PHY HPR0 Bit 10 TBR0 Bit 10 PHY_SEL ISOLATE Interface Source GM_MODE GM_MODE Input This input pin selects between the MDC/MDIO command and control interface and the SPI interface normally available in the GPSI mode. This pin must be connected to either VDD or VSS. Changing the state of this pin is prohibited. Managed Mode 1 1 1 0 0 0 0 0 0 1 1 1 1 Hi Z 1 Mbps HomePNA 10BASE-T Non Valid GM_MODE 0 0 1 MII/GPSI 1 0 X Data Interface MII GPSI GPSI Command and Control Interface MDC/MDIO SPI MDC/MDIO 0 1 0 External Control Mode 1 1 1 1 1 0 Don't Care 0 0 1 10BASE-T 1 Mbps HomePNA Hi Z Note: GM_MODE = 1 overrides the value on the MII/GPSI configuration pin. 1 1 PHY_AD PHY Address Input Sets bit 2 of the PHY Address field. The PHYs have default MII address of 0x00 (0000b) for the 1 Mbps HomePNA PHY and 0x01 (0001b) for the 10BASE-T PHY. If this bit is set, the address for the HomePNA PHY is 0x02 (00010b) and 0x03 (00011b) for the 10BASE-T PHY. Board Interface LED_COL LED_COL Output This output is designed to directly drive an LED. COL low indicates that a collision has been detected on the currently active PHY. An internal pulse stretching circuit will ensure that the minimum output pulse is approximately 100 ms. ISOLATE Isolate Input In an environment that utilizes the MII or the SPI command and control interface (managed mode), this pin must be held HIGH. In an environment that does not use the MII or the SPI command and control interface (external control mode), this pin enables the data interface when set to a LOW, and forces the interface into a high impedance state when held HIGH. This pin functions in conjunction with the PHY_SEL pin and HPR0, bit 10, and TBR0, bit 10. LED_ACTIVITY LED_ACTIVITY Output This output is designed to directly drive an LED. ACTIVITY low indicates that there is receive or transmit activity on the network of the currently active PHY. An internal pulse stretching circuit will ensure that the minimum output pulse is approximately 100 ms. PHY_SEL PHY Select Input In an environment that utilizes the MII or the SPI command and control interface (managed mode), this pin must be held LOW. In an environment that does not use LED_LINK LED_LINK Output This output is designed to directly drive an LED. LINK low indicates that a valid link has been detected on the currently active PHY. 18 Am79C901A PRELIMINARY LED_SPEED LED_SPEED Output This output is designed to directly drive an LED. SPEED low indicates that the HomePNA PHY is currently in the high-speed mode. When operating in the 10BASE-T mode this output will be held high. TXCLK Transmit Data Clock Output TXCLK provides the timing reference for transfer of the transmitted data. TXCLK is driven by the device and operates at a maximum frequency of 10 MHz. TXEN Transmit Enable Input TXEN indicates when the MAC device is presenting valid transmit data on the TXDAT pin. TXEN must be asserted with the first bit of preamble and remain asserted throughout the duration of the packet until it is deasserted prior to the first TXCLK following the final bit of the frame. TXEN transitions are synchronous to TXCLK. LED_POWER LED_POWER Output This output is designed to directly drive an LED. POWER low indicates that the HomePNA PHY is currently in high-power mode. When operating in the 10BASE-T mode this output will be held high. RESET RESET Input The RESET is an active-low, asynchronous RESET signal. This signal must be held low for a minimum of 5 s and requires 60 s for recovery after the rising edge of RESET. SPI Interface (Slave Mode Only) SCLK SPI Clock Input SCLK is driven from the controlling device as a timing reference for transfer of information on the SDI and SDO signals. The maximum clock frequency is 2.5 MHz. GPSI Interface RXDAT Receive Data Output RXDAT is the serial data received from the selected port. Data on RXDAT is driven on the falling edge of RXCLK. CS SPI Chip Select Input This pin is used to enable the Am79C901A for slave mode transfers. When this pin is inactive (HIGH), the device ignores SCLK and SDI inputs and holds SDO in high-impedance. RXCLK Receive Data Clock Output RXCLK provides the timing reference for transfer of the receive data. RXCLK is driven by the device and operates at a maximum frequency of 10 MHz. SDI SPI Serial Data In Input This data line provides input data from the master device to the Am79C901A. The data presented on this pin is latched on the rising edge of SCLK. RXCRS Receive Carrier Sense Output The RXCRS pin is active during receive or transmit activity for the HomePNA PHY or during receive (based on TBR17, bit 2) for the 10BASE-T PHY. SDO SPI Serial Data Out Output T hi s d a ta l in e pr ovi d e s ou t pu t d a ta f ro m th e Am79C901A to the master device. To provide for a robust interface, this data is driven on the rising edge of SCLK. CLS Collision Output This signal is asserted whenever a collision is detected on the transmit and receive path of the selected port. This signal will also be asserted for ~1 s within 40 s after the negation of the TXEN signal in support of the SQE test. The SQE functionality may be controlled via TBR17, bit 11, and HPR16, bit 12. MII Interface RX_CLK Receive Clock Output RX_CLK is a clock input that provides the timing reference for the transfer of the RX_DV, RXD[3:0], and R X_ER signal s from th e Am 79C901 A device. RX_CLK will provide a nibble rate clock. It operates at a maximum frequency of 2.5 MHz. TXDAT Transmit Data Input TXDAT is the serial data driven from the MAC. Data on TXDAT is latched on the falling edge of TXCLK. Am79C901A 19 PRELIMINARY RXD[3:0] Receive Data Output RXD[3:0] is the nibble-wide receive data bus. Data o n RX D [3 : 0] i s d r i ve n o n t h e fa l l i n g e d g e o f RX_CLK. RXD[3:0] should be ignored while RX_DV is deasserted. TXD[3:0] Transmit Data Input TXD[3:0] is the nibble-wide data bus. Valid data is generated on TXD[3:0] on every rising edge of TX_CLK while TX_EN is asserted. While TX_EN is deasserted, TXD[3:0] values are ignored. TXD[3:0] transitions are latched on the falling edge of TX_CLK. RX_DV Receive Data Valid Output RX_DV is an output used to indicate that valid received data is being presented on the RXD[3:0] pins and RX_CLK is synchronous to the receive data. RX_DV will be asserted prior to the RX_CLK rising edge, when the first nibble of the Start of Frame Delimiter (SFD) is driven on RXD[3:0], and will remain asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0]. RX_DV will be deasserted prior to the RX_CLK rising edge which follows this final nibble. RX_DV transitions are driven on the falling edge of RX_CLK. TX_EN Transmit Enable Input TX_EN indicates that the MAC device is presenting valid transmit data on the TXD[3:0] bus. TX_EN must be asserted with the first nibble of preamble and remains asserted throughout the duration of the packet until it is deasserted prior to the first TX_CLK following the final nibble of the frame. TX_EN transitions are latched on the falling edge of TX_CLK. MDC Management Data Clock Input MDC is the non-continuous clock input that provides a timing reference for bits on the MDIO pin. During MII management port operations, MDC runs at a nominal frequency of 2.5 MHz. CRS Carrier Sense Output The CRS pin is active during receive or transmit activity for the HomePNA PHY or during receive (based on TBR17, bit 2) for the 10BASE-T PHY. MDIO Management Data Input/Output Input/Output MDIO is a bidirectional MII management port data pin. MDIO is an input during the header portion of the management frame transfers and during the data portion of write operations. MDIO is an output during the data portion of read operations. The MDIO pin should be externally pulled up to VDD with a 1.5 k 5% resistor. COL Collision Output This signal is asserted whenever a collision is detected on the transmit and receive path of the selected port. This signal will also be asserted for ~1 s within 40 s after the negation of the TXEN signal in support of the SQE test. The SQE functionality may be controlled via TBR17, bit 11, and HPR16, bit 12. RX_ER Receive Error Output RX_ER is an output for the 10BASE-T PHY that indicates that the transceiver device has detected a coding error in the receive data frame currently being transferred on the RXD[3:0] pins. RX_ER is ignored while RX_DV is deasserted. Special code groups generated on RXD while RX_DV is deasserted are ignored (e.g., bad SSD in TX and idle in T4). RX_ER transitions are synchronous to RX_CLK. IEEE 1149.1 (JTAG) Test Access Port Interface TCK Test Clock Input TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency of up to 10 MHz. TCK has an internal pull-up resistor. TDI Test Data In Input TDI is the test data input path to the Am79C901A PHY. The pin has an internal pull-up resistor. TX_CLK Transmit Clock Output TX_CLK is a clock output that provides the timing reference for the transfer of the TXD[3:0] and TX_ER signals from the Am79C901A device. TX_CLK provides a nibble rate clock. TDO Test Data Out Output TDO is the test data output path from the Am79C901A PHY. The pin is tri-stated when the JTAG port is inactive. 20 Am79C901A PRELIMINARY TMS Test Mode Select Input A serial input bit stream on the TMS pin is used to define the specific boundary scan test to be executed. The pin has an internal pull-up resistor. XTAL1 Crystal Oscillator In Input The internal clock generator utilizes either a 20-MHz crystal that is attached to pins XTAL1 and XTAL2 or a 60-MHz clock source connected to XTAL1. This pin is not 5 V tolerant, and the 60 MHz clock source should be from a 3.3 V source. Ethernet Network Interfaces TX Serial Transmit Data Output These pins carry the transmit output data and are connected to the transmit side of the magnetics module. XTAL2 Crystal Oscillator Out Output The internal clock generator utilizes a 20-MHz crystal that is attached to pins XTAL1 and XTAL2. In XCLK mode, this pin should be left unconnected. RX Serial Receive Data Input These pins accept the receive input data from the magnetics module. Power Supply DVDD Digital Power (5 Pins) +3.3 V Power These pins are the power supply pins that are used to provide power to the digital portions of the design. All DVDD pins must be connected to a +3.3 V supply. IREF Internal Current Reference Input This pin serves as a current reference for the integrated 1/10 PHY. It must be connected to GND through a 12.1 k resistor (1%). AVDD Analog Power (7 Pins) +3.3 V Power These pins are the power supply pins that are used to provide power to the analog portions of the design. All AVDD pins must be connected to a +3.3 V supply. HomePNA PHY Network Interface HRTXRXP/HRTXRXN Serial Receive Data Input/Output These pins accept the receive input data from the magnetics module and carry the transmit output data. A 102- resistor should be placed between these pins. DVSS Digital Ground (6 Pins) Ground These pins are the ground connections for the digital portions of the design. Clock Interface XCLK/XTAL External Clock/Crystal Select Input When HIGH, an external 60-MHz clock source is selected bypassing the crystal circuit and clock trippler. When LOW, a 20-MHz crystal is used instead. Table 1 illustrates how this pin works. AVSS Analog Ground (4 Pins) Ground These pins are the ground connections for the analog portion of the design. Scan Test Interface TEN Test Enable Input The test enable pin is for factory use only. It must be connected to VSS for normal operation. Table 1. Input Pin XTAL1 XTAL1 Output Pin XTAL2 NC Clock Source Selection XCLK/XTAL 0 1 Clock Source 20-MHz Crystal 60-MHz Oscillator/ External CLK Source Am79C901A 21 PRELIMINARY BASIC FUNCTIONS Network Interfaces The Am79C901A PHY contains an integrated 1 Mbps home networking PHY and a 10BASE-T PHY. This device is compliant with the HomePNA specification 1.0 and IEEE 802.3 specification. The integrated HomePNA transceiver is a physical layer device that enables data networking at speeds up to 1 Mbps over existing residential phone wiring regardless of topology and without disrupting telephone (POTS) service. The integrated Ethernet transceiver is a physical layer device suppor ting the IEEE 802.3 standard for 10BASE-T. It provides all of the PHY layer functions required to support 10 Mbps data transfer speeds. The 10BASE-T PHY suppor ts both half-duplex and full-duplex operation. H_RESET or S_RESET. The following is a description of each type of RESET operation. H_RESET Hardware Reset (H_RESET) is a reset operation that has been initiated by the proper assertion of the RESET pin of the Am79C901A device. When the minimum pulse width timing as specified in the RESET pin description has been satisfied, an internal reset operation will be performed. H_RESET will program all of the registers to their default value. S_RESET In a software reset (S_RESET), programming bit 15 of HPR0 to 1 will reset all the registers in the 1 Mbps HomePNA PHY (HPRs), and programming bit 15 of TBR0 to 1 will reset TBR4, TBR7, TBR17, and TBR24 in the 10BASE-T PHY. These bits are self-clearing. PHY Data Interfaces The Am79C901A PHY has both GPSI and MII-compatible data interfaces. In addition, a special mode, GM_MODE, allows access to the MDC/MDIO command and control interface while in the GPSI mode. For more information, see the Pin Descriptions and the Detailed Functions sections. DETAILED FUNCTIONS GPSI Interface The seven signals that comprise the GPSI are TXCLK, TXEN, TXDAT, RXCLK, RXCRS, RXDAT, and CLS. Of these, only TXEN and TXDAT are inputs to the PHY; the other five are outputs from the PHY. These signals behave differently depending on which operation is currently happening in the PHY. The operations of the PHY are as follows: Idle (no activity in either direction), RXPKT (receiving data), and TXPKT (transmitting data). The subsequent subsections analyze each GPSI-related state of the PHY in detail. Reset There are two different types of RESET operations that may be perfor med on the Am79C901A device, TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS 22304B-3 Note: RXCLK and TXCLK are synchronized to the same phase. All other signals are inactive. The two clock signals toggle for an overall period of 583.3ns (about 1.7 MHz). Figure 1. Idle State 22 Am79C901A PRELIMINARY TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS 22304B-4 Note: RXCLK becomes disabled as soon as RXCRS is asserted. Figure 2. RXPKT - RXCRS Asserted TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS 22304B-5 Note: RXCLK and TXCLK are unrelated to each other during this time. When a symbol has been received and decoded, RXCLK toggles in order to shift out the three to six bits encoded in the symbol. The middle portion of this diagram shows the end of the preamble, followed by an SFD and the beginning of the data. RXCRS will fall after the last received symbol. Once RXCRS falls, RXCLK and TXCLK are toggled continuously for 96 cycles, after which the PHY returns to the Idle state. Figure 3. RXPKT - RXCRS Cleared Am79C901A 23 PRELIMINARY TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS Note: Once TXEN is asserted, the PHY stops RXCLK, asserts RXCRS, and toggles TXCLK. Figure 4. TXPKT - TXEN Asserted 22304B-6 TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS 22304B-7 Note: TXCLK continues to toggle until the SFD is observed, as shown in the first section of the above diagram. At this point, TXCLK is disabled (low) until the AID header has been transmitted on the wire (or until a CLS has been detected). At this time RXCLK starts toggling, thereby, shifting 32 bits of preamble and SFD back to the MAC. Sometime later, the TXCLK restarts as symbols get sent onto the wire in an analogous manner as RXCLK during packet reception. Figure 5. TXPKT - RXCLK Active 24 Am79C901A PRELIMINARY TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS 22304B-8 Note: Once TXEN is cleared, the last symbol gets encoded and transmitted, the looped-back data is presented back to the MAC, and RXCRS falls. Once RXCRS falls, TXCLK and RXCLK toggle for 96 clocks, after which the system returns to the Idle state. Figure 6. TXPKT - TXEN Cleared TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS 22304B-9 Note: CLS will be asserted some time after the preamble and SFD have been clocked in. TXCLK and RXCLK are then clocked until RXCRS drops. TXEN drops about 32 clocks after CLS was asserted. RXCRS and CLS are dropped together after more than 500 clocks (about 120 s). TXCLK and RXCLK keep toggling for approximately another 100 clock cycles, when the system returns to the Idle state. Figure 7. TXPKT - CLS Asserted Am79C901A 25 PRELIMINARY TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS 22304B-10 Note: CLS may be asserted up to 120 s after RXCRS has been asserted. Once CLS has been asserted, TXCLK and RXCLK run until 96 cycles after CLS and RXCRS are cleared. It can take a maximum of approximately 60 s for RXCRS to clear. Figure 8. RXPKT - CLS Asserted Table 2. Condition Idle (excluding IPG time) Preamble (first 64 bits of TX MAC frame) Data (throughout the data phase) IPG (96 bit times following CRS ) GPSI Timing CLK Frequency 1.7 MHz CLK Period 583.3 ns 233.3 ns 100 ns 10 s 233.3 ns 4.3 MHz opcode, followed by an 10-bit register address and 2 bits of end delimiter. If the operation is a write, the data bits are written into the desired register. If the operation is a read, then these data bits are ignored. The SDO pin will shift out 16 data bits representing the contents of the register referenced by the address field for read operations. All commands must be initiated with a high-to-low transition on the CS pin. Only one command can be sent in one CS cycle. For assistance in debugging access to the SPI interface, an error code is driven onto the SDO. If there is less than 32 bits of SCLK during the time that CS is asserted, the error code field of SDO on the next command will indicate AAAA. When there is an incorrect opcode in the command on SDI AAAA will be immediately driven out on SDO until CS deasserts. If there are more than 32 clock cycles while CS is low, the first 32 are assumed to contain the data, and the additional clock bits and associated data are ignored. In this case, the SDO might generate AAAA under the additional clock bits. See Figure 9. 1.0 MHz avg. 4.3 MHz Note: During the AID interval, TXCLK and RXCLK stop for up to 140 s. Serial Peripheral Interface (SPI-Slave) Mode When MII/GPSI is set to 0, the device is in "SPI" mode. The device acts as an SPI slave peripheral in this mode of operation. Commands are issued to the device by asserting the CS signal (active low), shifting in an 4-bit SCLK CS SDI SDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 Op Codes Error Code Address Data In Data Out 22304B-11 Figure 9. Operation of the SPI Interface 26 Am79C901A PRELIMINARY Table 3. SPI Op Codes SDI Op Codes ST READ WRITE 01 01 OP 10 01 PHYADD AAAAA AAAAA SDO Error Code READ WRITE 0000 = No Error/AAAA = Error Detected 0000 = No Error/AAAA = Error Detected Data Out D15...D0 Don't Care Address REGADD RRRRR RRRRR ED 10 10 Don't Care D15.........D0 Data In Start Frame CS SCLK SDI SDO 1 2 Read Command End Delimiter 3 4 15 16 17 18 31 32 First Data Bit Last Data Bit 22304B-12 Figure 10. SPI Read Operation SCLK CS SDI SDO 1 2 3 4 5 6 7 8 9 10 11 12 13 Op Codes Error Code = 0 Address 22304B-13 Figure 11. Aborted Operation of the SPI Interface SCLK CS SDI SDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 Op Codes Address Error Code = AAAA Data In Data Out 22304B-14 Figure 12. First Operation Following an Abort Am79C901A 27 PRELIMINARY SCLK CS SDI SDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 Op Codes Address Error Code = 0 Data In Data Out 22304B-15 Figure 13. Normal Operation MII-Compatible Interface for HomePNA PHY The control and data signals that are utilized in the MIIcompatible interface of the 1 Mbps HomePNA PHY function in an manner that is identical to that as defined in the 802.3u specification. The signals RX_CLK and TX_CLK function in a slightly different manner in that they operate at a reduced data rate and that these clock signals do not run at a constant rate due to the RLL25TM encoding scheme. See Table 4. The signals TX_CLK and RX_CLK will toggle at a rate of approximately 428 kHz during idle time. When the TX_EN signal is asserted to indicate the beginning of a transmission, the clock rate will enter the preamble phase. Once the SFD has been detected and the HomePNA PHY has begun the transmission of the HomePNA header, the clock enters the data phase. When the TX_EN signal is deasserted to indicate the ending of a transmission, TX_CLK is halted until the RXDATA path detects the end of the packet. At this time, the clock rate is increased to the IPG data rate for 96 bit times and then returns to the Idle state. Table 4. Condition Idle (excluding IPG time) MII-Compatible Timing CLK Period 2333.34 ns 933.33 ns 400 ns - 40 s 933.33 ns CLK Frequency 428.6 kHz 1.07 MHz 250 kHz avg. 1.07 MHz MII-Compliant Interface for 10BASE-T PHY The MII interface is fully IEEE 802.3u-compliant when the 10BASE-T PHY is selected. The management interface specified in Clause 22 of the IEEE 802.3u standard provides for a simple two wire, serial interface to connect a management entity and a managed PHY for the purpose of controlling the PHY and gathering status information. The two lines are Management Data Input/Output (MDIO) and Management Data Clock (MDC). A station management entity, which is attached to multiple PHY entities, must have prior knowledge of the appropriate PHY address for each PHY entity. The management interface physically transports management information across the MII. The information is encapsulated in a frame format as specified in Clause 22 of the IEEE 802.3u standard and is shown in Table 5. Preamble (first 64 bits of TX MAC frame) Data (throughout the data phase) IPG (96 bit times following CRS) Note: During the AID interval, TX_CLK and RX_CLK stop for up to 140 s. Figure 14 and Figure 15 represent the signal relationships when the MII-compatible data interface is utilized. Table 5. PRE READ WRITE 1...1 1...1 ST 01 01 OP 10 01 MII Control Frame Format REGADD RRRRR RRRRR TA Z0 10 DATA D15.........D0 D15.........D0 IDLE Z Z PHYADD AAAAA AAAAA 28 Am79C901A PRELIMINARY The operation field (OP) follows the start field (ST). The OP indicates whether the operation is a read or a write operation. The PHY address (PHYADD) and the register address (REGADD) that were programmed follow this. A bus turnaround field (TA) follows the REGADD field. During the read operation, the bus TA field is used to determine if the PHY is responding properly to the read request. The final field is the idle field, and it is required to allow the drivers to turn off. The PHYADD field, which is five bits wide, allows 32 unique PHY addresses. The managed PHY layer device that is connected to a station management entity via the MII interface has to respond to transactions addressed to the PHY's address. A station management entity attached to multiple PHYs is required to have prior knowledge of the appropriate PHY address. For more information, see the IEEE 802.3 specification and the MII pin descriptions. Idle TX_CLK Preamble Data TX_EN TXD 55 D CRS RX_CLK RX_DV RXD COL 55 55 55 D 2 22304B-16 Figure 14. MII Start of Transmission Am79C901A 29 PRELIMINARY IPG TX_CLK 96 Bit Times TX_EN Idle TXD data CRS RX_CLK RX_DV RXD data data 55 55 COL If SEQ is enabled 22304B-17 Figure 15. MII End of Transmission 30 Am79C901A PRELIMINARY 1 Mbps HomePNA PHY The integrated HomePNA transceiver is a physical layer device supporting HomePNA specification 1.0 for home phoneline networking. It provides all of the PHY layer functions required to support 1 Mbps data transfer speeds over existing residential phone wiring. All data bits are encoded into the relative time position of a pulse with respect to the previous one. The waveform on the wire consists of a 7.5 MHz carrier sinusoid enclosed within an exponential (bell shaped) envelope. The waveform is produced by generating four 7.5 MHz square wave cycles and passing them through an external bandpass filter. The HomePNA PHY frame consists of a HomePNA header that replaces the normal Ethernet 64-bit preamble and delimiter. The frame header is prepended to a standard Ethernet packet starting with the destination address and ending with the CRC. Only the PHY layer and its parameters are modified from that of the standard Ethernet implementation. The HomePNA PHY layer is designed to operate with a standard Ethernet MAC layer controller implementing all the CSMA/CD protocol features. The frame begins with a characteristic SYNC interval that delineates the beginning of a HomePNA frame followed by an Access ID (AID) which encodes 8 bits of AID and 4 bits of control word. The AID is used to detect collisions and is dynamically assigned, while the control word carries speed and power information. The AID is followed by a silence interval, then 32 bits of data reserved for PHY layer communication. These bits are accessible via internal registers and are for future use. Data encoding consists of two symbol types: an AID symbol and a data symbol. The AID symbol is always transmitted at the same speed and encodes 2 bits that determine the pulse position (one of four) relative to the previous pulse. These bits are transmitted LSB first. The access symbol interval is fixed. The data symbol interval is variable. The arriving bit stream is blocked into from 3-bit to 6-bit blocks according to a proprietary (RLL25) algorithm. The bits in each block are then used to encode a data symbol. Each symbol consists of a Data Inter Symbol Blanking Interval (DISBI) and then a pulse at one of 25 possible positions. The bits in the data block determine the pulse position. Immediately after the pulse a new symbol interval begins. During the DISBI the receiver ignores all incoming pulses to allow network reflections to die out. Any station may be programmed to assume the role of a PHY master and remotely command, via the control word, the rest of the units on the network to change their transmit speed or power level. Many of the framing parameters are programmable in the HomePNA PHY and will allow modifications to transmission speed center frequency as well as noise and reflection rejection algorithms. Two default speeds are provided, low at 0.7 Mbps and high at 1 Mbps. HomePNA PHY Medium Interface Framing The HomePNA frame on the phone wire network consists of a header generated in the PHY prepended to an IEEE 802.3 Ethernet data packet received from the MAC layer. See Figure 16. When transmitting on the phone wire pair, the HomePNA PHY first receives an Ethernet MAC frame from the MAC. The 8 octets of preamble and delimiter are stripped off and replaced with the HomePNA PHY header described below, then transmitted on the home network with the LSB of each symbol being transmitted first. During a receive operation, the reverse process is executed. When a HomePNA PHY frame is received by the PHY, the header is stripped off and replaced with the 4 octets of preamble and delimiter of the IEEE 802.3 Ethernet MAC frame specification and then passed on to the MAC layer. Am79C901A 31 PRELIMINARY HomePNA Header SYNC interval AID blanking interval Fixed 14.93 s 60 tics 01 Access ID Silence PCOM 4 Ethernet Packet Destination Source Length 6 6 2 ETHERNET MAC and DATA max 1500 CRC 4 AID blanking interval 11 AID blanking interval 10 AID blanking interval 00 AID blanking interval 01 AID blanking interval 00 Silence interval 32 bits PCOM Ethernet Packet 20 tics 66 tics pulse potential pulse position 129 tics ACCESS ID Symbol 5 129 tics ACCESS ID Symbol 6 129 tics ACCESS ID Symbol 7 Data symbols 129 tics SYNC Symbol 0 129 tics ACCESS ID Symbol 1 129 tics ACCESS ID Symbol 2 129 tics ACCESS ID Symbol 3 129 tics ACCESS ID Symbol 4 30.75 s @ 1 Mbps ACCESS ID interval Fixed 120.39 s Example Access ID of 01110100 and control word 0100 HomePNA PHY Header 151.14 s @ 1 Mbps 1 Tic = 116.6667 ns = receiver blanking interval Note: Using default configurations. 22304B-18 Figure 16. HomePNA PHY Framing HomePNA PHY Symbol Waveform All HomePNA PHY symbols are composed at the transmitter of a silence interval and a pulse formed of an integer number of cycles (TX_PULSE_CYCLES_P/N in HPR29) of a square wave of frequency (CENTER_FREQUENCY TX_PULSE_WIDTH in HPR29) that has been filtered with an external bandpass filter. Data is encoded in the time interval from the preceding pulse. These symbols are described in the following sections. Symbol 0 (SYNC interval) SYNC Transmit Timing: The SYNC interval (AID symbol 0) delineates the beginning of a HomePNA PHY frame and is composed of a SYNC_START pulse, followed by a SYNC_END pulse, after a fixed silence interval as shown in Figure 17. Timing for this (AID symbol 0) starts (TIC = 0) at the beginning of the SYNC_START pulse. The SYNC_END pulse starts at TIC = 126. At TIC = 129, this AID symbol 0 ends and the next AID symbol begins, with the symbol timing reference reset to TIC = 0. No information bits are coded in the SYNC (AID symbol 0 interval). SYNC Receive Timing: As soon as the SYNC_START pulse is detected the receiver disables (blanks) further detection until time TIC = 61, after which detection is re-enabled for the next received pulse. The receiver allows for jitter by establishing a window around each legal pulse position. This asymmetrical window is two TICS wide on one side of the position and one TIC wide on the other. A SYNC_END pulse that arrives outside the window of the legal TIC = 126 is considered a noise event which is used in setting the adaptive squelch level, aborts the packet, and sets the receiver in search of a new SYNC_START pulse and SYNC interval. If it is a transmitting station, the COLLISION event is asserted as described in the Collisions section. Table 6. HomePNA PHY Pulse Parameters Value 7.5 4 Tolerance 500 PPM - Unit MHz Cycles Parameter CENTER_FREQUENCY CYCLES_PER_PULSE Time Interval Unit HomePNA PHY time intervals are expressed in Time Interval Clock (TIC) units. One TIC is defined as 7/60E6 seconds or approximately 116.7 ns. Access ID Intervals A HomePNA frame begins with an Access ID (AID) interval which is composed of eight equally spaced subintervals termed AID symbols 0 through 7 as shown in Figure 17. An AID symbol is 129 TICs long. Transmit timing is shown in Figure 17; receive timing in Figure 18. Timing starts at the beginning of each AID symbol at TIC = 0 and ends at TIC = 129. 32 Am79C901A PRELIMINARY Transmitter AID Symbol 0 pulse 0 pulse 1 AID Symbol 1 pulse 2 shown in position 1 AID Symbol 2 SYNC_START TIC=0 SYNC_END TIC=126 TIC=129 and TIC=0 AID_Position_0 TIC=66 AID_Position_1 TIC=86 AID_Position_2 TIC=106 AID_Position_3 TIC=126 TIC=129 and TIC=0 22304B-19 Figure 17. AID Symbol Transmit Timing Receiver D slice threshold pulse 0 AID Symbol 0 pulse 1 AID Symbol 1 pulse 2 shown in position 1 AID Symbol 2 Detected envelope END_RCV_BLANK SYNC_START TIC=0 TIC=129 and TIC=0 AID_Position_0 TIC=66 AID_Position_1 TIC=86 AID_Position_2 TIC=106 SYNC_END TIC=126 AID_Position_3 TIC=126 TIC=129 and TIC=0 AID_GUARD_INTERVAL 22304B-20 Figure 18. AID Symbol Receive Timing The SYNC interval is followed by six AID symbols (symbols 1 through 6). Transmit timing is shown in Figure 17; receive timing in Figure 18. Data is encoded in the relative position of each pulse with respect to the previous one. A pulse may occur at one, and only one, of the four possible positions within an AID symbol yielding two bits of data coded per AID symbol. The decoded bits from the AID symbols 1 to 4 produce eight bits of Access ID which is used to identify individual HomePNA stations and to detect collisions. The MSB is encoded in AID Symbol 1 and is the leftmost bit in Table 7. Table 7. Pulse Position 1 2 3 4 Access ID Symbol Pulse Positions and Encoding TICs from Beginning of AID Symbol Bit Encoding 66 86 106 126 00 01 10 11 Am79C901A 33 PRELIMINARY The next two AID symbols (5 and 6) encode four bits of control word information. The MSB is encoded in AID Symbol 5. Control word messages are described further in the Mode Interface section. AID Transmit Timing: The transmitter encodes the Access ID in a pulse position in each 129 TIC interval. Each AID symbol interval must have only one pulse. Pulse transmission must start in only one of the four possible positions (measured from the beginning of the Access ID symbol) defined in Table 7. AID Receive Timing: The receiver allows for jitter by establishing a window around each legal pulse position. This asymmetrical window is two TICS wide on one side of the position and one TIC wide on the other. A pulse that arrives outside of the legal AID positions is considered a COLLISION event. Collisions A Collision is detected only during Access ID and silent intervals (AID symbols 0 through 7). In general during a collision, a transmitting station will read back an AID value that does not match its own, recognize the event as a collision, and alert other stations with a JAM signal. Non-transmitting stations may also detect some collisions by interpreting received non-conforming AID pulses as collisions. With two transmitters colliding, each transmitter normally blanks its receive input immediately after transmitting (and simultaneously receiving) a pulse. Therefore, only when a transmitting station receives pulses in a position earlier than the position it transmitted will it recognize it as a pulse transmitted by another station and signal a collision. For this reason, guaranteed collision detection is possible only as long as the spacing between successive possible pulse positions in an AID symbol (20 TICs or 2.3 s) is greater than the roundtrip delay between the colliding nodes. At approximately 1.5 ns propagation delay per foot, the maximum distance between two HomePNA units must not be greater than 500 feet for collision detection purposes (1.5 s roundtrip delay plus margin). The following criteria must be met to guarantee reliable collision detection: At least one HomePNA station of a colliding group must always detect a collision when the delay between the beginning of its transmitted packet and the beginning of the received colliding packet is between -1.5 s and +1.5 s. In general, any received pulse at a HomePNA station that does not conform to the pulse position requirements of AID symbols 0 through 7 shall indicate a collision on the wire. When a transmitting station senses a collision, it emits a JAM signal to alert all other stations to the collision. The following conditions signify a COLLISION event: 1. A HomePNA station receives an AID that does not match the one being sent. 2. A HomePNA station receives a pulse outside the AID_GUARD INTERVAL in AID intervals 0 to 7. 3. A HomePNA station receives a pulse inside the SILENT_INTERVAL (AID symbol 7). As in all cases, pulses received during a blanking interval are ignored. Passive stations (stations not actively transmitting during the collision) cannot reliably detect collisions. Therefore, once a collision is detected by a transmitting station, the station must inform the rest of the stations of the collision with a JAM pattern described below. Only a transmitting station emits a JAM signal. Once a collision is detected, the COLLISION signal to the MAC interface is asserted and is not reset until the MAC deactivates the TXEN signal. JAM Signal A JAM pattern consists of 1 pulse every 32 TICs and continues until at least the end of the AID intervals. After the AID interval, the JAM pattern will continue until TXEN from the MAC is deactivated. Access ID Values The access ID values for stations are randomly picked by each individual station from the set of AID numbers described in the management section. During operation, each HomePNA station monitors HomePNA frames received on the wire. If it detects another HomePNA station using the same AID, it will select a new random AID. Silence Interval (AID symbol 7) The Access ID symbols are followed by a fixed silence interval of 129 TICs. The receive blanking interval is the same as that of the AID symbols (1 through 6). Any pulses detected in the silence interval are considered a COLLISION event for transmitting stations and are handled as described in the Collisions section. Data Symbols Data symbols encode data for a much higher transmission rate, and they do not allow collision detection. 34 Am79C901A PRELIMINARY Data Transmit Timing A data symbol interval begins with the start of transmission of a pulse as shown in Figure 19. Transmit Symbol timing (in TICs) is measured from this point (TIC = 0). Depending on the data code, the next pulse may begin at any PULSE_POSITION_N where N = 0 to 24. Each position is separated from the previous one by one TIC. PULSE_POSITION_0 occurs at a value defined in Table 8 which determines the transmission speed. When a pulse begins transmission, the previous symbol interval ends and a new one begins immediately. Table 8. Blanking Interval Speed Settings Nominal Data Rate 0.7 Mbps 1.0 Mbps PULSE_POSITION_0 Value (in TICs) 44 28 Speed Setting LOW_SPEED HIGH_SPEED Transmitter Symbol 1 Pulse 0 Data Blanking interval (DISBI) Pulse 1 Symbol 2 1 TIC Pulse 2 START_TX_PULSE TIC=0 END_TX_PULSE time PULSE_POSITION_0 time Position 1 Position n1 n=0-24 Position 0 Position 1 Position n2 22304B-21 Figure 19. Transmit Data Symbol Timing Data Receive Timing The incoming waveform is formed from the transmitted pulse along with any distortions and reflections that occur in the wiring network. The receiver detects the point at which the envelope of the received waveform crosses a set threshold. See Figure 20. Immediately after the threshold crossing, the receiver disables any further detection for a period ISBI-3 TICs (HPR28, ISBI_SLOW or ISBI_FAST) starting with the detection of the pulse peak. The receiver is then re-enabled for pulse detection. Upon reception of the next pulse, the receiver measures the elapsed time from the previous pulse. This value is then placed in the nearest pulse position bin (one of 25) where pulse position 0 is at PULSE_POSITION_0 and each subsequent position is spaced one TIC from the previous one as defined in the Data Transmit Timing section. Data symbol intervals are therefore variable and depend on the encoded data. Receiver Symbol 1 Data slice threshold Pulse 0 Detected Envelope Pulse 1 Symbol 2 Pulse 2 END_DATA_BLANK egin of receive anking interval Position 0 Position 1 Position n1 Position 0 Position 1 Position n2 22304B-22 Figure 20. Receive Symbol Timing Am79C901A 35 PRELIMINARY Data Symbol RLL25 Encoding The RLL25 code is the version of TM32 that was developed for the HomePNA PHY. It produces the highest bit rate for a given value of ISBI and TIC size. In a manner similar to run length limited disk coding, RLL25 encodes data bits in groups of varying sizes, specifically: 3, 4, 5, and 6 bits. Pulse positions are assigned to the encoded bit groups in a manner, which causes more data bits to be encoded in positions that are farther apart. This keeps both the average and minimum bit rates higher. Data symbol RLL25 codes data by traversing a tree as illustrated in Figure 21. Assuming that successive data bits are encoded and labeled A, B, C, D,..., etc., the encoding process begins at the root node and proceeds as follows: 1. If the first bit (bit A) is a one, the next three bits (B, C, and D) select which one of the eight positions 1-8 is transmitted. The encoding process then continues at the root node. 2. If bit A is a zero and bit B is a one, the next three bits (C, D, and E) select which one of the eight positions 9-16 is transmitted. The encoding process then continues at the root node. 3. If bit A is a zero, bit B is a zero, and bit C is a one, the next three bits (D, E, and F) select which one of the eight positions 17-24 is transmitted. The encoding process then continues at the root node. 4. Finally, if bits A, B, and C are all zeros, position 0 is transmitted. The encoding process then continues at the root node. As a result, Symbol 0 encodes the 3-bit data pattern 000, positions 1-8 encode the 4-bit data pattern 1BCD, positions 9-16 encode the 5-bit data pattern 01CDE, and positions 17-24 encode the 6-bit data pattern 001DEF. If the data encoded is random, 50% of the positions used will be for 4-bit patterns, 25% will be for 5bit patterns, 12.5% will be for 6-bit patterns, and 12.5% will be for 3-bit patterns. Mode Interface The HomePNA PHY may be managed from either of two interfaces (the managed parameters vary depending on the interface): 1. Remote Control-Word management commands embedded in the HomePNA AID header on the wire network. 2. Management messages from a local management entity. Data stream from MAC controller Start: Examine the next bits to be encoded Encoded and sent A B C D E F Awaiting coding and transmission A=? 0 1 Send symbol 1-8 1 B C D These select position 1 - 8 1 Send symbol 9-16 0 1 C D E B=? 0 These select position 9 - 16 1 Send symbol 17-24 0 0 1 D E F C=? 0 These select position 17- 24 1 Send symbol 0 0 0 0 22304B-23 Figure 21. RLL 25 Coding Tree 36 Am79C901A PRELIMINARY Header AID Remote Control Word Commands Stations may be configured either as master stations or as slave stations. Only one master may exist on a given HomePNA segment or network over which the HomePNA PHY header is preserved. The master station may send commands embedded in the HomePNA header control word to remotely set various parameters of the remote slave stations. Stations are identified via the AID as follows: 1. The master station is identified on the HomePNA wire network with an AID of FFh. 2. A slave is identified with an AID of 00h to EFh. 3. AID values of F0h to FEh are reserved for future use. Once a command has been transmitted, the master station will revert to a slave AID, so that subsequent control words are not interpreted by the slave stations as new commands. Master mode is entered by writing to the PHY control register (HPR16, bits 8 to 11) and is exited upon the completion of the command sequence. A valid master remote command consists of three HomePNA frames with an AID of FFh. Since the HomePNA PHY header is prepended to packets received from the MAC, as well as any1Home packets, packets from the master station may be separated by intervals during which other (slave) stations may transmit their frames. A remote master Control Word command will be recognized and executed by a HomePNA PHY when it receives three consecutive valid HomePNA frames with an AID of FFh. Valid commands are as follows: 1. SET_POWER: Commands slave stations to set their transmit level to a prescribed level until another master command is received. 2. SET_SPEED: Commands slave stations to set their transmit speed to a prescribed value until another master command is received. The control word bit encoding and possible values are described in Table 9. Table 9. AID 5 5 Master Station Control Word Functions Bit No. LSB MSB Command Function 0 = version 0 0 = Set to low-power transmit mode. 1 = Set to high-power transmit mode. 0 = Set to low-speed transmit mode. 1 = Set to high-speed transmit mode. Reserved 6 6 LSB MSB Slave stations transmit the following status messages in the HomePNA header control word of all outgoing frames: 1. VERSION_STATUS: The HomePNA PHY version of the slave station. The receiving station must revert to this version to interpret the packet. 2. POWER_STATUS: The transmit power level of the transmitting slave station for the current frame. All HomePNA units support both LOW_POWER and HIGH_POWER modes of operation. 3. SPEED_STATUS: The transmit speed of the slave station for the current frame. Receiving stations will adjust their receiver parameters to correctly interpret this frame. The slave control word bit encoding is identical to the master control word format. 1 Mbps HomePNA PHY Loopback The HomePNA PHY is capable of supporting internal loopback only. Internal Loopback In internal loopback, the transmitted data is returned to the receive data bus without transmitting data on the network. The MAC must be programmed to support full-duplex operation and is responsible for comparing the transmitted data to that received. Internal loopback is accomplished by setting the "enable loopback mode" in HPR0, bit 14, to 1. any1Home Link Detection While consuming minimal network resources, AMD's innovative any1Home Link Detection Packet provides a means to indicate to the MAC, and thus the upper layers of the system protocol, that a valid network (as defined by HomePNA) has been detected. The Link Detection Packet is also capable of detecting a network failure and allows the upper layer protocol to take corrective action. Thus, the any1Home Packet provides link indication that the MAC requires for compliance to the Microsoft PC98, PC99, and HomePNA revision 1.1 requirements without utilizing resources from the upper layers of the system protocol Am79C901A 37 PRELIMINARY The any1Home link packet consists of valid AID and PCOM fields followed by four bytes of data. The receiving node's MAC will interpret this packet as a runt frame and will not forward the frame to upper layers, thus ensuring that no system resources are required. T h e A m 79 C 9 0 1A Ho m e P HY wi l l t ra n sm it t h e any1Home Link Packet as a result of not transmitting a normal Data packet within the last 400 ms time period. Similarly, the HomePHY will determine that it is not connected to a valid network (a link down state) after not receiving any Data or Link packets for a period greater than four seconds. The any1Home Link detection status is reported via the LED_LINK output pin and in the HomePNA PHY Status Register (HPR1, bit 2). See Table 18. Clock Data Clock Data Manchester Encoder Manchester Decoder Squelch Circuit 10BASE-T PHY The 10BASE-T transceiver incorporates the physical layer function, including both clock recovery (ENDEC) and transceiver function. Data transmission over the 10BASE-T medium requires an integrated 10BASE-T MAU. The transceiver meets the electrical requirements for 10BASE-T as specified in IEEE 802.3i. The transmit signal is filtered on the transceiver to reduce harmonic content per IEEE 802.3i. Since filtering is performed in silicon, external filtering modules are not needed. The 10BASE-T PHY transceiver receives 10 Mbps data from the MAC across the MII at 2.5 million nibbles per second (parallel), or 10 million bits per second (serial) for 10BASE-T. It then Manchester encodes the data before transmission to the network. The 10BASE-T block consists of the following sub-blocks: -- Transmit Process -- Receive Process -- Interface Status -- Collision Detect Function -- Jabber Function -- Reverse Polarity Detect Refer to Figure 22 for the 10BASE-T block diagram. TX Driver RX Driver TX RX 22304B-24 Figure 22. 10BASE-T Transmit and Receive Data Paths Twisted Pair Transmit Function Data transmission over the 10BASE-T medium requires use of the integrated 10BASE-T MAU and uses the differential driver circuitry on the TX pins. TX is a differential twisted-pair driver. When properly terminated, TX will meet the transmitter electrical requirements for 10BASE-T transmitters as specified in IEEE 802.3, Section 14.3.1.2. The load is a twisted pair cable that meets IEEE 802.3, Section 14.4. Twisted Pair Receive Function The RX+ port is a differential twisted-pair receiver. When properly terminated, the RX+ port will meet the electrical requirements for 10BASE-T receivers as specified in IEEE 802.3, Section 14.3.1.3. The receiver has internal filtering and does not require external filter modules or common mode chokes. Signals appearing at the RX differential input pair are routed to the internal decoder. The receiver function meets the propagation delays and jitter requirements specified by the 10BASE-T standard. The receiver squelch level drops to half its threshold value after unsquelch to allow reception of minimum amplitude signals and to mitigate carrier fade in the event of worst case signal attenuation and crosstalk noise conditions. 38 Am79C901A PRELIMINARY Twisted Pair Interface Status The Am79C901A device will power up in the Link Fail state. The Auto-Negotiation algorithm will apply to allow it to enter the Link Pass state. In the Link Pass state, receive activity which passes the pulse width/amplitude requirements of the RX inputs will cause the PCS Control block to assert the Carrier Sense (CRS) signal at the MII interface. A collision would cause the PCS Control block to assert Carrier Sense (CRS) and Collision (COL) signals at the MII. In the Link Fail state, this block would cause the PCS Control block to deassert Carrier Sense (CRS) and Collision (COL). In jabber detect mode, this block would cause the PCS Control block to assert the COL signal at the MII and allow the PCS Control block to assert or deassert the CRS pin to indicate the current state of the RX pair. If there is no receive activity on RX, this block would cause the PCS Control block to assert only the COL pin at the MII. If there is RX activity, this block would cause the PCS Control block to assert both COL and CRS at the MII. Collision Detect Function Simultaneous activity (presence of valid data signals) from both the internal encoder transmit function and the twisted pair RX pins constitutes a collision, thereby causing the PCS Control block to assert the COL pin at the MII. Jabber Function The Jabber function inhibits the 10BASE-T twisted pair transmit function of the Am79C901A device if the TX circuits are active for an excessive period (20-150 ms). This prevents one port from disrupting the network due to a stuck-on or faulty transmitter condition. If the maximum transmit time is exceeded, the data path through the 10BASE-T transmitter circuitry is disabled (although Link Test pulses will continue to be sent). The PCS Control block also asserts the COL signal at the MII and sets the Jabber Detect bit in Register 1 of the active PHY. Once the internal transmit data stream from the MENDEC stops, an unjab time of 250-750 ms will elapse before this block causes the PCS Control block to deassert the COL indication and re-enable the transmit circuitry. When jabber is detected, this block will cause the PCS Control block to assert the COL signal and allow the PCS Control block to assert or deassert the CRS signal to indicate the current state of the RX pair. If there is no receive activity on RX, this block causes the PCS Control block to assert only the COL signal at the MII. If there is RX activity, this block will cause the PCS Control block to assert both COL and CRS on the MII. Reverse Polarity Detect The polarity for 10BASE-T signals is set by reception of Normal Link Pulses (NLP) or packets. Polarity is locked, however, by incoming packets only. The first NLP received when trying to bring the link up will be ignored, but it will set the polarity to the correct state. The reception of two consecutive packets will cause the polarity to be locked, based on the polarity of the End of Transmit Data (ETD). In order to change the polarity once it has been locked, the link must be brought down and back up again. Auto-Negotiation The object of the Auto-Negotiation function is to determine the abilities of the devices sharing a link. After exchanging abilities, the Am79C901A device and remote link partner device acknowledge each other and make a choice of which advertised abilities to support. The Auto-Negotiation function facilitates an ordered resolution between exchanged abilities. This exchange allows both devices at either end of the link to take maximum advantage of their respective shared abilities. The Auto-Negotiation algorithm uses a burst of link pulses called Fast Link Pulses (FLPs). The burst of link pulses are spaced between 55 and 140 s so as to be ignored by the standard 10BASE-T algorithm. The FLP burst conveys information about the abilities of the sending device. The receiver can accept and decode an FLP burst to learn the abilities of the sending device. The link pulses transmitted conform to the standard 10BASE-T template. The device can perform Auto-Negotiation with reverse polarity link pulses. The Am79C901A device uses the Auto-Negotiation algorithm to select the type connection to be established according to the following priority: 10BASE-T full duplex, then 10BASE-T half-duplex. See Table 10. The Auto-Negotiation algorithm is initiated by the following events: Auto-Negotiation enable bit is set, hardware reset, soft reset, transition to link fail state (when Auto-Negotiation enable bit is set), or Auto-Negotiation restart bit is set. The result of the Auto-Negotiation process can be read from the status register (Summary Status Register, TBR24). By default, the link partner must be at least 10BASE-T half-duplex capable. The Am79C901A PHY can automatically negotiate with the network and yield the highest performance possible without software support. Table 10. Network Speed 20 Mbps 10 Mbps Auto-Negotiation Capabilities Physical Network Type 10BASE-T, Full Duplex 10BASE-T, Half Duplex Am79C901A 39 PRELIMINARY Auto-Negotiation goes further by providing a message-based communication scheme called Next Pages before connecting to the Link Partner. Soft Reset Function The PHY Control Register (TBR0) incorporates the soft reset function (bit 15). It is a read/write register and is self-clearing. Writing a 1 to this bit causes a soft reset. When read, the register returns a 1 if the soft reset is still being performed; otherwise, it is cleared to zero. Note that the register can be polled to verify that the soft reset has terminated. Under normal operating conditions, soft reset will be finished in 150 clock cycles. Soft reset only resets the 10BASE-T PHY unit registers to default values (some register bits retain their previous values). Soft reset does not reset the management interface. 10BASE-T Loopback The 10BASE-T PHY is capable of supporting two different types of loopback, referred to as internal and external loopback. Internal Loopback In internal loopback, the transmitted data is returned to the receive data bus without transmitted data appearing on the network. The MAC must be programmed to support full-duplex operation and is responsible for comparing the transmitted data to that received. Internal loopback is accomplished by setting the "enable loopback mode" in TBR0, bit 14, to 1. External Loopback External loopback is accomplished by the use of an exter nal shor ti ng plug. In this environm ent, the 10BASE-T PHY is left in through mode (i.e., enable loopback mode in TBR0 = 0), the MAC in full duplex. The transmitted data will then be looped back at the shorting plug into the receive circuitry and driven onto the receive data bus for the MAC to process and verify. Table 11. LED Output LED_COL LED_ACTIVITY LED_LINK LED_SPEED LED_POWER LED Default Configuration Indication Collision Activity Link Speed Power Driver Mode Open Drain - Active Low Open Drain - Active Low Open Drain - Active Low Open Drain - Active Low Open Drain - Active Low Pulse Stretch Enabled Enabled Not applicable Not applicable Not applicable IEEE 1149.1 (JTAG) Test Access Port Interface An IEEE 1149.1-compatible boundary scan Test Access Port is provided for board-level continuity test and diagnostics. All digital input, output, and input/output pins are tested. The following paragraphs summarize the IEEE 1149.1-compatible test functions implemented in the controller. Refer to the IEEE 1149.1 Boundary Scan Architecture document for details. Boundary Scan Circuit The boundary scan test circuit requires four pins (TCK, TMS, TDI, and TDO), defined as the Test Access Port (TAP). It includes a finite state machine (FSM), an instruction register, a data register array, and a power-on reset circuit. Internal pull-up resistors are provided for the TDI, TCK, and TMS pins. TAP Finite State Machine The TAP engine is a 16-state FSM driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power-on reset circuit is provided to ensure that the FSM is in the TEST_LOGIC_RESET state at power-up. Therefore, the TRST is not provided. The FSM is also reset when TMS and TDI are high for five TCK periods. Supported Instructions In addition to the minimum IEEE 1149.1 requirements (BYPASS, EXTEST, and SAMPLE instructions), two additional instructions (IDCODE and TRI_ST) are provided to further ease board-level testing. All unused instruction codes are reserved. See Table 12 for a summary of supported instructions. LED Support The controller can support up to five LEDs. LED outp u t s L E D _ C O L , L E D _ AC T I V I T Y, L E D _ L I N K , LED_SPEED, and LED_POWER allow for direct connection of an LED and its supporting pull-up device. The outputs are stretched to allow the human eye to recognize even short events that last only several microseconds. The five LED outputs are configured as shown in Table 11. 40 Am79C901A PRELIMINARY The main purpose of this is board-level testing. See Table 15. To force the output pins, use SAMPLE to load the BSR cells via the TDI pin and EXTEST to force the output. Program the output cells, and set the control cells to enable the output, or clear the control cells to float the output. To sample the chip inputs and outputs, use a SAMPLE command and cell values are shifted out through the TDO pin. Check the values in the input cells. Both input and output pins have input-type cells. Table 12. IEEE 1149.1 Supported Instruction Summary Selected Data Register BSR ID REG BSR Bypass Bypass Bypass Bypass Instruction Instruction Name Code Description EXTEST IDCODE SAMPLE TRI_ST BYPASS TRI_ST BYPASS 0000 0001 0010 0011 1111 0011 1111 External Test ID Code Inspection Sample Boundary Force TriState Force TriState Mode Test Normal Normal Normal Bypass Scan Normal Normal Table 15. BSR Cell No. 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 Boundary Scan Ring Order Cell Name XTAL_SEL_L CRS CRS CRS_COL_OEN COL COL TXD3_CSN TXD2 TXD1_SDI TXD0_TXDAT TX_EN TX_CLK_OEN TX_CLK TX_CLK GM_MODE RX_ER RX_ER PHY_SEL RX_CLK RX_CLK RX_DV_RXEN RX_DV_RXEN RXD_OEN RXD0_RXDAT RXD0_RXDAT RXD1 RXD1 RXD2 RXD2 RXD3 RXD3 LED_SPEED LED_SPEED LED_SPEED LED_POWER Bypass Scan Normal Cell Type1 IN IN OUT CO IN OUT IN IN IN IN IN CO IN OUT IN IN OUT IN IN OUT IN OUT CO IN OUT IN OUT IN OUT IN OUT CO IN OUT CO Pin No. 39 32 32 - 30 30 28 27 25 24 23 - 22 22 21 19 19 17 15 15 13 13 - 11 11 10 10 9 9 8 8 6 6 6 5 Instruction Register and Decoding Logic After the TAP FSM is reset, the IDCODE instruction is always invoked. The decoding logic gives signals to control the data flow in the data registers according to the current instruction. Boundary Scan Register Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the Serial Shift Stage and the Parallel Output Stage, respectively. There are four possible operation modes in the BSR cell shown in Table 13. Table 13. 1 2 3 4 BSR Mode Of Operation Capture Shift Update System Function Other Data Registers Other data registers are the following: 1. Bypass register (1 bit) 2. Device ID register (32 bits) (Table 14). Table 14. Bits 31-28 Bits 27-12 Bits 11-1 Bit 0 Version Part Number (1001 0000 0001 0000) Manufacturer ID. The 11-bit manufacturer ID code for AMD is 00000000001 in accordance with JEDEC publication 106-A. Always a logic 1 Device ID Register Boundary Scan Cells In Boundary Scan, most of the chip input and output latches are linked together to form a scan chain. Am79C901A 41 PRELIMINARY 18 17 LED_POWER LED_POWER IN OUT 5 5 BSR Cell No. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cell Name LED_ACTIVITY LED_ACTIVITY LED_ACTIVITY LED_COL LED_COL LED_COL LED_LINK LED_LINK LED_LINK MDC_SCLK MDIO MDIO MDIO_OEN ISOLATE PHY_AD MODE_MII RESET_L Cell Type1 CO IN OUT CO IN OUT CO IN OUT IN IN OUT CO IN IN IN IN Pin No. 3 3 3 2 2 2 1 1 1 68 66 66 - 65 64 63 61 Notes: 1. IN = input cells, samples the device inputs and internal outputs; OUT = output cells, drives the device outputs and internal inputs; and CO = control cells, controls the output enable. 2. BSR Cell 0 is closest to TDO. 3. Boundary register is 54 bits long. Data path starts from TDI to cell 53, cell 0 to TDO. 42 Am79C901A PRELIMINARY USER ACCESSIBLE REGISTERS The Am79C901A PHY has two types of user registers: 1 Mbps HomePNA PHY management registers (HPRs) and 10BASE-T PHY management registers (TBRs). 1 Mbps HomePNA PHY Management Registers (HPRs) The registers of the HomePNA PHY are accessible via the MII or the SPI interface. All reserved registers should not be written to, and reading them will return an undetermined value. Table 16 lists all the registers implemented in the HomePNA PHY. Table 16. Register Address 0 1 2 3 4 5 6 7 8-15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 Mbps HomePNA PHY Management Registers (HPRs) Name Control Register Status Register PHY_ID Register PHY_ID Register Auto-Negotiation Register Auto-Negotiation Register Auto-Negotiation Register Auto-Negotiation Register Reserved PHY Control Register Status/Control Register PHY TXCOMM Register PHY TXCOMM Register PHY RXCOMM Register PHY RXCOMM Register PHY AID Register PHY Noise Control Register PHY Noise Control 2 Register PHY Noise Statistics Register Event Status Register AID Control Register ISBI Control Register TX Control Register Drive Level Control Register Analog Control Register Basic/Extended B B E E E E E E E E E E E E E E E E E E E E E E E Symbol HPR0 HPR1 HPR2 HPR3 HPR4 HPR5 HPR6 HPR7 HPR8-HPR15 HPR16 HPR17 HPR18 HPR19 HPR20 HPR21 HPR22 HPR23 HPR24 HPR25 HPR26 HPR27 HPR28 HPR29 HPR30 HPR31 Default Value After H_RESET 0400h 0841h 0000h 6B91h 0021h 0000h 0000h 0000h - 0005h 000xh 0000h 0000h 0000h 0000h 0000h 03FFh F4xxh 03FFh 0000h 1440h 2C1Ch 0444h x549h C000h Am79C901A 43 PRELIMINARY HPR0: HomePNA PHY Control Register (Register 0) Table 17. HPR0: HomePNA PHY Control Register (Register 0) Read/ Write Default Value (hex) Bits Name 1 = RESET Description 15 RESET When read, 1= reset in process 0 = Normal operation ** Self Clearing after ~70 s R/W 0 14 13 12 Enable Loopback Mode Speed Selection Auto-Negotiation Enabled 1 = Loopback mode enable 0 = Loopback mode disable 0 = 10 Mbps 1 = Enabled 0 = Disabled 1 = Power down R/W R R 0 0 0 11 Power Down 0 = Normal operation (This bit is mirrored in PHY Control bit 4) R 0 10 Isolate 1 = Electrically isolates PHY from the MII/GPSI 0 = Normal operation 1 = Restart Auto-Negotiation R/W 1 9 Restart Auto-Negotiation 0 = Normal operation ** Self Clearing R 0 8 Duplex Mode 1 = Full-Duplex (for Loopback test only) 0 = Half-Duplex 1 = Enable COL test signal 0 = Disable COL test signal Write as 0, ignore on read R/W 0 7 6:0 Collision Test (Note 1) Reserved R/W R 0 0 Notes: 1. For collision test, the "enable loopback mode" bit must also be set to ensure that collision traffic is not imposed on the network. 2. R/W = Read/Write; R = Read only. 44 Am79C901A PRELIMINARY HPR1: HomePNA PHY Status Register (Register 1) Table 18. HPR1: HomePNA PHY Status Register (Register 1) Default Value (hex) 0 0 0 0 1 X Bits 15 14 13 12 11 10:7 Name 100BASE-T4 100BASE-X Full-Duplex 100BASE-X Half-Duplex 10 Mbps Full-Duplex 10 Mbps Half-Duplex Reserved Management Frame Preamble Suppression Description 0 = PHY not able to perform 100BASE-T4 0 = PHY not able to perform Full-Duplex 100BASE-X 0 = PHY not able to perform Half-Duplex 100BASE-X 0 = PHY not able to perform 10 Mbps in Full-Duplex 1 = PHY able to perform 10 Mbps in Half-Duplex Reads will produce undefined results 1 = PHY will accept management frames with Preamble suppressed 0 = PHY will not accept management frames with Preamble suppressed 1 = Auto-Negotiation completed 0 = Auto-Negotiation not completed 1 = Remote fault detected 0 = Normal operation 1 = PHY is able to perform Auto-Negotiation 0 = PHY is not able to perform Auto-Negotiation 1 = Link is up Read/Write R R R R R R 6 R 1 5 Auto-Negotiation Complete R 0 4 Remote Fault R 0 3 Auto-Negotiation Ability R 0 2 Link Status 0 = Link is down This bit will be RESET (latched low and re-enabled on Read). R 0 1 Jabber Detect 1 = Jabber condition detected 0 = Normal operation 1 = Extended Register capability 0 = Basic Register Set capability R 0 0 Extended Capability R 1 Am79C901A 45 PRELIMINARY HPR2 and HPR3: HomePNA PHY ID Registers (Registers 2 and 3) Table 19. HPR2: HomePNA PHY ID Register (Register 2) Read/ Write R Bits 15:0 Name PHY_ID MSB (31-16) Description Most significant bytes of the PHY_ID (Bits 3-18) Default Value (hex) 0000 Table 20. Bits 15:10 9:4 HPR3: HomePNA PHY ID Register (Register 3) Description IEEE Address (Bits 19-24) Manufacturer's Model Number Name PHY_ID LSB (15-10) PHY_ID LSB (9-4) Read/ Write R R Default Value (hex) 1A 39 1 (rev. A.1) 2 (rev. A.2) 3 (rev. A.3) 3:0 PHY_ID LSB (3-0) Revision Number R 46 Am79C901A PRELIMINARY HPR4: HomePNA PHY Auto-Negotiation Advertisement Register (Register 4) This register contains the advertised ability of the Am79C901A device. The purpose of this register is to advertise the technology ability to the link partner device. When this register is modified, Restart Auto-Negotiation (Register 0, bit 9) must be enabled to guarantee the change is implemented. Table 21. HPR4: HomePNA PHY Auto-Negotiation Advertisement Register (Register 4) Default Value (hex) 0 0 0 0 0 0 0 Bits 15 14 13 12:11 10 9 8 Name Next Page Reserved Remote Fault Reserved PAUSE Reserved Full-Duplex 100BASE-TX Half-Duplex 100BASE-TX Full-Duplex 10BASE-T Half-Duplex 10BASE-T Selector Field Description When set, the device wishes to engage in next page exchange. If cleared, the device does not wish to engage in next page exchange. Read/Write R R When set, a remote fault bit is inserted into the base link code word during the Auto-Negotiation process. When cleared, the base link code work will have the bit position for remote fault as cleared. R R This bit should be set if the PAUSE capability is to be advertised. R R This bit advertises Full-Duplex capability. When set, Full-Duplex capability is advertised. When cleared, Full-Duplex capability is not advertised. This bit advertises Half-Duplex capability for the Auto-Negotiation process. Setting this bit advertises Half-Duplex capability. Clearing this bit does not advertise Half-Duplex capability. This bit advertises Full-Duplex capability. When set, Full-Duplex capability is advertised. When cleared, Full-Duplex capability is not advertised. This bit advertises Half-Duplex capability for the Auto-Negotiation process. Setting this bit advertises Half-Duplex capability. Clearing this bit does not advertise Half-Duplex capability. The Am79C901A device is an IEEE 802.3 compliant device. R 7 R 0 6 R 0 5 4:0 R R 1 01 Am79C901A 47 PRELIMINARY HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register (Register 5) The Auto-Negotiation Link Partner Ability Register is Read Only. The register contains the advertised ability of the link partner. The bit definitions represent the received link code word. This register contains either the base page or the link partner's next pages. The values contained in these registers are only valid once AutoNegotiation has successfully completed, as indicated by bit 5 in HPR1, or if the Next Page exchange is used, after the Page Received (bit 1 of HPR6) has been set to logic one. Table 22. HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register - Base Page Format (Register 5) Default Value (hex) 0 0 0 0 0 Bits 15 14 13 12:5 4:0 Name Next Page Acknowledge Remote Fault Technology Ability Selector Field Description Link partner next page request Link partner acknowledgment Link partner remote fault request Link partner technology ability field Link partner selector field Read/Write R R R R R Table 23. HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register - Next Page Format (Register 5) Default Value (hex) 0 0 0 0 0 0 Bits 15 14 13 12 11 10:0 Name Next Page Acknowledge Message Page Acknowledge 2 Toggle Message Field Description Link partner next page request Link partner acknowledgment Link partner message page request 1 = Link partner can comply with the request 0 = Link partner cannot comply with the request Link partner toggle bit Link partner's message code Read/Write R R R R R R 48 Am79C901A PRELIMINARY HPR6: HomePNA PHY Auto-Negotiation Expansion Register (Register 6) The Auto-Negotiation Expansion Register provides additional information that aids the Auto-Negotiation process. The Auto-Negotiation Expansion Register bits are Read Only. Table 24. HPR6: HomePNA PHY Auto-Negotiation Expansion Register (Register 6) Default Value (hex) 0 0 Bits 15:5 4 Name Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Description Read/Write R 1 = Parallel detection fault 0 = No parallel detection fault 1 = Link partner is next page able 0 = Link partner is not next page able 1 = Am79C901A device channel is next page able 0 = Am79C901A device channel is not next page able 1 = A new page has been received 0 = A new page has not been received 1 = Link partner is Auto-Negotiation able 0 = Link partner is not Auto-Negotiation able R 3 R 0 2 R 0 1 Page Received Link Partner AutoNegotiation Able R 0 0 R 0 HPR7: HomePNA PHY Auto-Negotiation Next Page Register (Register 7) The Auto-Negotiation Next Page Register contains the next page link code word to be transmitted. On power-up the default value of 0x2001 represents a message page with the message code set to null. Table 25. HPR7: HomePNA PHY Auto-Negotiation Next Page Register (Register 7) Default Value (hex) 0 0 0 Bits 15 14 13 Name Next Page Reserved Message Page Description Am79C901A device channel next page request Read/Write R R Am79C901A device channel message page request 1 = Am79C901A device channel can comply with the request R 12 Acknowledge 2 Toggle Message Field 0 = Am79C901A device channel cannot comply with the request Am79C901A device channel toggle bit Message code field R 0 11 10:0 R R 0 000 Reserved Registers: HPR8 - HPR15 These registers should be ignored when read and should not be written to at any time. Am79C901A 49 PRELIMINARY HPR16: HomePNA PHY Control Register (Register 16) Table 26. HPR16: HomePNA PHY Control Register (Register 16) Read/ Write R/W Bits 15 Name Remote Command Description 1 = Ignore Remote Commands 0 = Normal operation Reads will produce undefined results. Should be written as 0. 1 = Disables the SQE heartbeat which occurs after each transmission. Default Value (hex) 0 14:13 Reserved R/W XX 12 SQE_TEST Disable 0 = The heartbeat assertion occurs on the COL pin approximately 1-5 s after transmission and for a duration of 1 s. 1 = Command low power 0 = Normal operation 1 = Command high power 0 = Normal operation 1 = Command low speed 0 = Normal operation 1 = Command high speed 0 = Normal operation 1 = Disable AID negotiation 0 = Normal operation 1 = Clear PHY event counter R/W 0 11 Command Low Power R/W 0 10 Command High Power R/W 0 9 Command Low Speed R/W 0 8 Command High Speed R/W 0 7 Disable AID Negotiation R/W 0 6 Clear PHY-Event Counter 0 = Normal operation **Self clearing after ~100 ns R/W 0 5 Disable Squelch adaptation 1 = Disable Squelch adaptation 0 = Normal operation 1 = Power down R/W 0 4 Power Down 0 = Normal operation (This bit is controlled by the HPR0, bit 11) R 0 3 2 Reserved High Speed Reads will produce undefined results 1 = Device is currently in High speed 0 = Device is currently in Low speed 1 = Device is currently in High power 0 = Device is currently in Low power Reads will produce undefined results R R/W X 1 1 0 High Power Reserved R/W R/W 0 X Note: Writes to bits 1 and 2 will affect speed and power on node only. 50 Am79C901A PRELIMINARY HPR17: HomePNA PHY Status/Control Register (Register 17) The HomePNA PHY Status/Control Register provides information regarding the global aspects of the operation of the PHY. Table 27. HPR17: HomePNA PHY Status/Control Register (Register 17) Default Value (hex) 00 Bits 15:13 Name Reserved any1Home_ Disable Description Test control bits. Reads will produce undefined results. Should be written as 0. 1 = any1Home Link packet disabled 0 = any1Home Link packet enabled Test control bits. Reads will produce undefined results. Should be written as 0. Test control bit. Reads will produce undefined results. Should be written as 0. 1 = Last packet received, was sent at High Power 0 = Last packet received, was sent at Low Power 1 = Last packet received, was sent at High Speed 0 = Last packet received, was sent at Low Speed 1 = Last packet received, was sent at Version XX 0 = Last packet received, was sent at Version 0 Test control bits. Reads will produce undefined results. Should be written as 0. Read/Write R 12 R/W 0 11:8 7 Reserved Reserved Received_Power R R 3 0 6 R 0 5 Received_Speed R 0 4 Received_Ver Reserved R 0 3:0 R X HPR18 and HPR19: HomePNA PHY TxCOMM Registers (Registers 18 and 19) Table 28. HPR18 and HPR19: HomePNA PHY TxCOMM Registers (Registers 18 and 19) Default Value (hex) 0000 Bits 15:0 Name PHY_TX_COMM (4) Description The 32-bit preamble transmitted on the HomePNA PHY. HPR18 contains the high word and HPR19 the low word. Read/Write R/W The 32-bit transmitted data field is to be used for outof-band communication between PHY management entities. No protocol for out-of-band management has been defined. Accessing the low word causes the PHY to send all-0 PCOMs until the high word has been accessed. Once accessed, the next transmitted packet will cause this register's contents to be shifted out in the PCOM field of the transmitted packet. Upon transmission, this register will read back as all 0s. A non-null transmitted PCOM will set the TxPCOM Ready bit in the Event Status Register (HPR26). An access to any of the two TxPCOM words will clear the TxPCOM Ready bit in the ISTAT register. Am79C901A 51 PRELIMINARY HPR20 and HPR21: HomePNA PHY RxCOMM Registers (Registers 20 and 21) Table 29. HPR20 and HPR21: HomePNA PHY RxCOMM Registers (Registers 20 and 21) Default Value (hex) 0000 Bits 15:0 Name PHY_RX_COMM (4) Description The 32-bit preamble received by the HomePNA PHY. HPR20 contains the high word and HPR21 the low word. Read/Write R The 32-bit received data field to be used for out-ofband communication between PHY management entities. No protocol for out-of-band management has been defined. Accessing the low word of the register is sufficient to ensure that subsequently received packets will not overwrite the register HPR22: HomePNA PHY AID Register (Register 22) Table 30. contents. A non-null received PCOM will set the RxPCOM Valid bit of the Event Status Register (HPR26). Accessing the high word of the register clears this bit and allows overwriting of the register by subsequent received packets. HPR22: HomePNA PHY AID Register (Register 22) Default Value (hex) Bits Name Description The Access ID of this PHY. Read/Write 15:8 PHY_AID If PHY_Control Disable AID Negotiation is set, then writes to this bit will have no effect. An 8-bit counter that records the number of noise events detected. Overflows are held as FFh. Can be cleared by setting bit 6 of HPR16. R/W 00 7:0 Noise Events R/W 00 The PHY's AID address is used for collision detection. Unless bit 7 of the CONTROL register is set, the PHY is assured to select a unique AID address. Addresses above EFh are reserved. Address FFh is defined to indicate a remote command. HPR23: HomePNA PHY Noise Control Register (Register 23) Table 31. HPR23: HomePNA PHY Noise Control Register (Register 23) Read/ Write Default Value (hex) Bits Name Description If the input NOISE measurement (HPR25, bits 15:8) exceeds the PEAK measurement (HPR25, bits 7:0), this value is loaded into the NOISE Level register HPR25, bits 15:8. If the input NOISE measurement (HPR25, bits 15:8) exceeds the PEAK measurement (HPR25, bits 7:0), this value is loaded into the NOISE Level register HPR25, bits 7:0. 15:8 Noise Floor R/W 03 7:0 Noise Ceiling R/W FF 52 Am79C901A PRELIMINARY HPR24: HomePNA PHY Noise Control 2 Register (Register 24) Table 32. Bits Name HPR24: HomePNA PHY Noise Control 2 Register (Register 24) Description Sets the attack characteristics of the NOISE algorithm. High nibble sets number of noise events needed to raise the NOISE level immediately, while the low nibble is the number of noise events needed to raise the level at the end of an 870 ms period. Reads will produce undefined results. Read/ Write Default Value 15:8 Noise Attack R/W F4 7:0 Reserved R XX HPR25: HomePNA PHY Noise Statistics Register (Register 25) Table 33. HPR25: HomePNA PHY Noise Statistics Register (Register 25) Read/ Write Default Value (hex) Bits Name Description This is the digital value of the SLICE_LVL_NOISE output. It is effectively a measure of the noise level on the wire and tracks noise by counting the number of false triggers of the NOISE comparator in an 800 ms window. When auto-adaptation is enabled (bit 5 of the PHY_Control Register is false), this register is updated with the current NOISE count every 50 ns. When adaptation is disabled, this register may be written to and is used to generate both the SLICE_LVL_NOISE and SLICE_LVL_DATA signals. This is a measurement of the peak level of the last valid (non-collision) AID received. 15:8 Noise Level R/W 03 7:0 Peak Level R/W FF Am79C901A 53 PRELIMINARY HPR26: HomePNA PHY Event Status Register (Register 26) Table 34. HPR26: HomePNA PHY Event Status Register (Register 26) Read/ Write R Bits 15:10 9 Name Reserved RxPCOM Description Default Value (hex) 0 0 Indicates a valid RxPCOM. An access to the RxCOM MSB Register 18 will clear this bit. Indicates a valid TxPCOM. Any access to the TxCOM registers (Registers 20 and 21) will clear this bit. Reads will produce undefined results. Should be written as 0. Status is cleared by writing a 0. Status is cleared by writing a 0. A valid remote command was received. Status is cleared by writing a 0. A remote command has been sent. Status is cleared by writing a 0. R 8 TxPCOM R 0 7:4 3 2 1 Reserved Packet Received Packet Transmitted Remote Command Received R R/W R/W R/W X 0 0 0 0 Remote Command Sent R/W 0 HPR27: HomePNA PHY AID Control Register (Register 27) The HomePNA AID Control Register reports the state of each event source. Any bit may be written and so facilitate software-stimulated event testing. Table 35. HPR27: HomePNA PHY AID Control Register (Register 27) Read/ Write R/W R/W Bits 15:8 7:0 Name AID_INTERVAL AID_ISBI Description This value defines the number of TCLKs (116.6 ns) separating AID symbols. This value defines the number of TCLKs (116.6 ns) separating AID symbol 0. Default Value (hex) 14 40 54 Am79C901A PRELIMINARY HPR28: HomePNA PHY ISBI Control Register (Register 28) Table 36. HPR28: HomePNA PHY ISBI Control Register (Register 28) Read/ Write R/W Bits 15:8 Name ISBI_SLOW Description This value defines the number of TCLKs (116.6 ns) separating data pulses for Symbol 0 in low-speed mode. This value defines the number of TCLKs (116.6 ns) separating data pulses for Symbol 0 in high-speed mode. Default Value (hex) 2C 7:0 ISBI_FAST R/W 1C HPR29: HomePNA PHY TX Control Register (Register 29) Table 37. HPR29: HomePNA PHY TX Control Register (Register 29) Read/ Write R/W Bits 15:8 Name TX_PULSE_WIDTH Description This value defines the duration of a transmit pulse in OSC cycles (16.7 ns). This will effectively determine the transmit spectrum of the PHY. This value defines the number of pulses that will be driven onto the HRTXRX_N pin. This value defines the number of pulses that will be driven onto the HRTXRX_P pin. Default Value (hex) 04 7:4 3:0 TX_PULSE_CYCLES_N TX_PULSE_CYCLES_P R/W R/W 4 4 HPR30: HomePNA PHY Drive Level Control Register (Register 30) Table 38. HPR30: HomePNA PHY Drive Level Control Register (Register 30) Read/ Write R R/W R/W Bits 15:12 11:6 5:0 Name Reserved High Level Control Low Level Control Description Reserved. Must be written as 0. Read = X. Defines the drive level that will be utilized in the High Power mode. Defines the drive level that will be utilized in the Low Power mode. Default Value (hex) XX 15 09 Am79C901A 55 PRELIMINARY HPR31: HomePNA PHY Analog Control Register (Register 31) Table 39. HPR31: HomePNA PHY Analog Control Register (Register 31) Read/ Write Default Value (hex) Bits Name Description Global output slope adjustment. These bits control the number of current sources enabled for transmit. Each bit represents a single current source. Thus 10101 enables three current sources as does 11100. Reserved. Must be written as 0. 1 = Link Status bit will be held valid 0 = Normal operation Reserved. Must be written as 0. 15:11 Level_Adjust R/W 18 10:8 7 6:0 Reserved Force_Link_Valid Reserved R/W R/W R/W 0 0 0 10BASE-T PHY Management Registers (TBRs) The Am79C901A home networking device supports the MII basic register set and extended register set. Both sets of registers are accessible through the MII management interface or via the SPI interface. As specified in the IEEE standard, the basic register setStatus Register (Register 1). The extended register set consists of the Control Register (Register 0) and the consists of Registers 2 to 31 (decimal). Table 40 lists all the 10BASE-T registers implemented in the device. All the reserved registers should not be written to, and reading them will return an undetermined value. Table 40. Register Address 0 1 2 3 4 5 6 7 8:15 16 17 18 19 20:23 24 25:31 10BASE-T PHY Management Registers (TBRs) Name Basic/Extended B B E E E E E E E E E E E E E E Symbol TBR0 TBR1 TBR2 TBR3 TBR4 TBR5 TBR6 TBR7 TBR8-TBR15 TBR16 TBR17 TBR18 TBR19 TBR20-TBR23 TBR24 TBR25-TBR31 Default Value After H_RESET 1500h 1xx9h 0000h 6B71h 0061h 0000h 0004h 2001h - 0000h 0001h - - - 0000h - PHY Control Register PHY Status Register PHY Identifier Register PHY Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Reserved Status and Enable Register PHY Control/Status Register Reserved PHY Management Extension Register Reserved Summary Status Register Reserved 56 Am79C901A PRELIMINARY TBR0: 10BASE-T PHY Control Register (Register 0) Table 41. TBR0: 10BASE-T PHY Control Register (Register 0) Read/Write (Note 1) Default Value (hex) Bits Name When write Description 1 = PHY software reset 15 Soft Reset (Note 2) 0 = Normal operation When read 1 = Reset in process 0 = Reset done R/W, SC 0 14 Enable Loopback Mode Speed Selection (Note 3) Auto-Negotiation Enable 1 = Loopback mode enable 0 = Loopback mode disable 1 = 100 Mbps (not available) 0 = 10 Mbps 1 = Enable Auto-Negotiation 0 = Disable Auto-Negotiation 1 = Power down 0 = Normal operation 1 = Electrically isolates PHY from the MII/GPSI 0 = Normal operation 1 = Restart Auto-Negotiation 0 = Normal operation 1 = Full-Duplex 0 = Half-Duplex 1 = Enable COL signal test 0 = Disable COL signal test Write as 0, ignore on read R/W 0 13 R 0 12 R/W 1 11 Power Down Isolate (Note 4) Restart Auto-Negotiation Duplex Mode (Note 3) Collision Test (Note 5) Reserved R/W 0 10 R/W 1 9 R/W, SC 0 8 R/W 1 7 6:0 R/W R 0 0 Notes: 1. R/W = Read/Write, SC = Self Clearing, R = Read only. 2. Soft Reset does not reset the PDX block. Refer to the Soft Reset section for details. 3. Bits 8 and 13 have no effect if Auto-Negotiation is enabled (Bit 12 = 1). 4. If the ISOL pin of the chip and the Isolate bit in Register 0 is 1, this bit will be set. 5. The "enable loopback mode" bit must also be set to ensure that collision traffic is not imposed on the network. Am79C901A 57 PRELIMINARY TBR1: 10BASE-T Status Register (Register 1) The Status Register identifies the physical and AutoNegotiation capabilities of the local PHY. This register is read only; a write will have no effect. See Table 42. Table 42. TBR1: 10BASE-T PHY Status Register (Register 1) Read/Write (Note 1) R Bits 15 Name 100BASE-T4 100BASE-X Full-Duplex 100BASE-X Half-Duplex 10 Mbps Full-Duplex Description 1 = 100BASE-T4 able 0 = Not 100BASE-T4 able 1 = 100BASE-X full-duplex able 0 = Not 100BASE-X full-duplex able 1 = 100BASE-X half-duplex able 0 = Not 100BASE-X half-duplex able 1 = 10 Mbps full-duplex able 0 = Not 10 Mbps full-duplex able 1 = 10 Mbps half-duplex able 0 = Not 10 Mbps half-duplex able Ignore when read 1 = PHY can accept management (mgmt) frames with or without preamble 0 = PHY can only accept mgmt frames with preamble 1 = Auto-Negotiation completed 0 = Auto-Negotiation not completed 1 = Remote fault detected 0 = No remote fault detected 1 = PHY able to auto-negotiate, 0 = PHY not able to auto-negotiate 1 = Link is up 0 = Link is down 1 = Jabber condition detected 0 = No jabber condition detected 1 = Extended register capabilities 0 = Basic register set capabilities only Default Value (hex) 0 14 13 R R 0 0 12 R 1 11 10:7 10 Mbps Half-Duplex Reserved Management Frame Preamble Suppression R R 1 X 6 R 1 5 Auto-Negotiation Complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability R R, LH (Note 1) 0 4 3 2 1 0 0 1 0 0 1 R R, LL (Note 1) R R Note: 1. LH = Latching High, LL = Latching Low. 58 Am79C901A PRELIMINARY TBR2 and TBR3: 10BASE-T PHY Identifier Register (Registers 2 and 3) Registers 2 and 3 contain a unique PHY identifier, consisting of 22 bits of the organizationally unique IEEE identifier, a 6-bit manufacturer's model number, and a 4-bit manufacturer's revision number. The most significant bit of the PHY identifier is bit 15 of register 2; the least significant bit of the PHY identifier is bit 0 of register 3. Register 2, bit 15, corresponds to bit 3 of the IEEE identifier and register 2, bit 0, corresponds to bit 18 of the IEEE identifier. Register 3, bit 15, corresponds to bit 19 of the IEEE identifier and register 3, bit 10, corresponds to bit 24 of the IEEE identifier. Register 3, bits 9-4, contain the manufacturer's model number and bits 3-0 contain the manufacturer's revision number. These registers are shown in Table 43 and Table 44. Table 43. Bits 15:0 TBR2: 10BASE-T PHY Identifier Register (Register 2) Description IEEE Address (bits 3-18); Register 2, bit 15 is MSB of PHY Identifier Read/ Write R Name PHY_ID[31-16] Default Value (hex) 0000 Table 44. Bits 15:10 9:4 3:0 TBR3: 10BASE-T PHY Identifier Register (Register 3) Description IEEE Address (bits 19-24) Manufacturer's Model Number (bits 5-0) Revision Number (bits 3-0); Register 3, bit 0, is LSB of PHY Identifier Read/ Write R R R Name PHY_ID[15-10] PHY_ID[9-4] PHY_ID[3-0] Default Value (hex) 1A 37 01 Am79C901A 59 PRELIMINARY TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) This register contains the advertised ability of the Am79C901A home networking device. The purpose of this register is to advertise the technology ability to the link partner device. See Table 45. W hen th is reg ister is m odifi ed, Restar t AutoNegotiation (Register 0, bit 9) must be enabled to guarantee the change is implemented. Table 45. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) Read/ Write R/W R Bits 15 14 Name Next Page Reserved Description When set, the device wishes to engage in next page exchange. If cleared, the device does not wish to engage in next page exchange. Default Value (hex) 0 0 13 Remote Fault When set, a remote fault bit is inserted into the base link code word during the Auto-Negotiation process. When cleared, the base link code work will have the bit position for remote fault as cleared. R/W 0 12:11 10 9 8 Reserved PAUSE Reserved Full-Duplex 100BASE-TX R 0 0 0 0 This bit should be set if the PAUSE capability is to be advertised. R/W R This bit advertises Full-Duplex capability. When set, Full-Duplex capability is advertised. When cleared, Full-Duplex capability is not advertised. This bit advertises Half-Duplex capability for the Auto-Negotiation process. Setting this bit advertises Half-Duplex capability. Clearing this bit does not advertise Half-Duplex capability. This bit advertises Full-Duplex capability. When set, Full-Duplex capability is advertised. When cleared, Full-Duplex capability is not advertised. This bit advertises Half-Duplex capability for the Auto-Negotiation process. Setting this bit advertises Half-Duplex capability. Clearing this bit does not advertise Half-Duplex capability. The 10BASE-T PHY of the Am79C901A home networking device is an 802.3 compliant device. R 7 Half-Duplex 100BASE-TX R 0 6 Full-Duplex 10BASE-T R/W 1 5 Half-Duplex 10BASE-T R/W 1 4:0 Selector Field R 01 60 Am79C901A PRELIMINARY TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) The Auto-Negotiation Link Partner Ability Register is Read Only. The register contains the advertised ability of the link partner. The bit definitions represent the received link code word. This register contains either the base page or the link partner's next pages. The values contained in these registers are only valid once AutoNegotiation has successfully completed, as indicated by bit 5 in TBR1, or if the Next Page exchange is used after the Page Received (TBR6, bit 1) has been set to logic one. See Table 46 and Table 47. Table 46. Bits 15 14 13 12:5 4:0 TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page Format Name Next Page Acknowledge Remote Fault Technology Ability Selector Field Description Link partner next page request Link partner acknowledgment Link partner remote fault request Link partner technology ability field Link partner selector field Read/ Write R R R R R Default Value (hex) 0 0 0 0 0 Table 47. Bits 15 14 13 12 11 10:0 TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Next Page Format Name Next Page Acknowledge Message Page Acknowledge 2 Toggle Message Field Description Link partner next page request Link partner acknowledgment Link partner message page request 1 = Link partner can comply with the request 0 = Link partner cannot comply with the request Link partner toggle bit Link partner's message code Read/ Write R R R R R R Default Value (hex) 0 0 0 0 0 0 Am79C901A 61 PRELIMINARY TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) The Auto-Negotiation Expansion Register provides additional information which aids the Auto-Negotiation process. The Auto-Negotiation Expansion Register bits are Read Only. See Table 48. Table 48. Bits 15:5 4 TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) Description Read/ Write R Name Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Default Value (hex) 0 0 1 = Parallel detection fault 0 = No parallel detection fault 1 = Link partner is next page able 0 = Link partner is not next page able 1 = Am79C901A device channel is next page able 0 = Am79C901A device channel is not next page able 1 = A new page has been received 0 = A new page has not been received R, LH 3 R 0 2 R R, LH 1 1 Page Received 0 0 Link Partner ANEG 1 = Link partner is Auto-Negotiation able Able 0 = Link partner is not Auto-Negotiation able R 0 TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7) The Auto-Negotiation Next Page Register contains the next page link code word to be transmitted. On power-up the default value of 2001h represents a message page with the message code set to null. See Table 49. Table 49. Bits 15 14 13 12 11 10:0 TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7) Description Am79C901A device channel next page request Read/ Write R/W R Name Next Page Reserved Message Page Acknowledge 2 Toggle Message Field Default Value (hex) 0 0 1 0 0 001 Am79C901A device channel message page request 1 = Am79C901A device channel can comply with the request 0 = Am79C901A device channel cannot comply with the request Am79C901A device channel toggle bit Message code field R/W R/W R R/W Reserved Registers (Registers 8-15, 18, 20-23, and 25-31) The Am79C901A device contains reserved registers at addresses 8-15, 18, 20-23, and 25-31. These registers should be ignored when read and should not be written to at any time. 62 Am79C901A PRELIMINARY TBR16: 10BASE-T Status and Enable Register (Register 16) The status bits indicate when there is a change in the Link Status, Duplex Mode, Auto-Negotiation status, or Speed status. Register 16 contains the status and enable bits. The status is always updated whether or not the enable bits are set. When a status change occurs, the system will need to read this register to clear the status bits. See Table 50. Table 50. Bits 15:14 TBR16: 10BASE-T Status and Enable Register (Register 16) Description Read/ Write R Name Reserved Default Value (hex) 0 13 Status Test Enable (Note 1) 1 = When this bit is set, setting bits 12:9 of this register will cause a condition that will set bits 4:1 accordingly. The effect is to test the register bits with a forced interrupt condition. 0 = Bits 4:1 are only set if the interrupt condition (if any bits in 12:9 are set) occurs. R/W 0 12 Link Status Change Enable Duplex Mode Change Enable Auto-Negotiation Change Enable Speed Change Enable 1 = Link Status change enable 0 = This interrupt is masked 1 = Duplex Mode change enable 0 = This interrupt is masked 1 = Auto-Negotiation change enable 0 = This interrupt is masked 1 = Speed change enable 0 = This interrupt is masked 1= Global interrupt enable 0 = This interrupt is masked R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 7:5 4 Global Enable Reserved Link Status Change R/W R 0 0 0 1 = Link Status has changed on a port 0 = No change in Link Status 1 = Duplex Mode has changed on a port 0 = No change in Duplex mode 1 = Auto-Negotiation status has changed on a port 0 = No change in Auto-Negotiation status 1 = Speed status has changed on a port 0 = No change 1 = Indicates a change in status of any of the above interrupts 0 = Indicates no change in Interrupt status R, LH 3 Duplex Mode Change R, LH 0 2 Auto-Negotiation Change R, LH 0 1 Speed Change R, LH 0 0 Global R, LH 0 Note: All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared. Am79C901A 63 PRELIMINARY TBR17: 10BASE-T PHY Control/Status Register (Register 17) This register is used to control the configuration of the 10 Mbps PHY of the Am79C901A home networking device. See Table 1. Table 1. TBR17: 10BASE-T PHY Control/Status Register (Register 17) Default Value (hex) 00 0 Bits 15:14 13 Name Reserved Force Link Good Enable Description Read/Write R 1 = Link status forced to link up state 0 = Link status is determined by the device 1 = Link pulses sent from the 10BASE-T transmitter are suppressed 0 = Link pulse enabled (normal operation) 1 = Disables the SQE heartbeat which occurs after each 10BASE-T transmission 0 = The heartbeat assertion occurs on the COL pin approximately 1 s after transmission and for a duration of 1 s R/W 12 Disable Link Pulse R/W 0 11 SQE_TEST Disable R/W 0 10 9 8:7 6 Reserved Jabber Detect Disable Reserved Receive Polarity Reversed Auto Receive Polarity Correction Disable R 0 0 00 0 1 = Disable jabber detect 0 = Enable jabber detect R/W R 1 = Receive polarity of the 10BASE-T receiver is reversed 0 = Receive polarity is correct 1 = Polarity correction circuit is disabled for 10BASE-T 0 = Self correcting polarity circuit is enabled 1 = 10BASE-T receive squelch thresholds are reduced to allow reception of frames which are greater than 100 meters 0 = Squelch thresholds are set for standard distance of 100 meters 1 = TX outputs not active 0 = Transmit valid data 1 = CRS is asserted when transmit or receive medium is active 0 = CRS is asserted when receive medium is active R 5 R/W 0 4 Extended Distance Enable R/W 0 3 TX_DISABLE R/W 0 2 1 0 TX_CRS_EN Reserved PHY Isolated R/W R 0 0 1 1 = 10BASE-T PHY is isolated 0 = 10BASE-T PHY is enabled R Note: For these loopback paths, the data is also transmitted out of the MDI pins (TX). 64 Am79C901A PRELIMINARY TBR19: 10BASE-T PHY Management Extension Register (Register 19) Table 2 contains the PHY Management Extension Register (Register 19) bits. Table 2. Bits 15:6 TBR19: 10BASE-T PHY Management Extension Register (Register 19) Description Write as 0; ignore on read 1 = Last management frame was invalid (opcode error, etc.) 0 = Last management frame was valid PHY Address defaults to 000X1 Read/Write R Name Reserved Default Value (hex) 0 5 Mgmt Frame Format R 0 4:0 PHY Address X = Value on pin PHY_ADD (i.e., 00001 or 00011) R 01/03 TBR24: 10BASE-T Summary Status Register (Register 24) The Summary Status register is a global register containing status information. This register is Read Only and represents the most important data which a single register access can convey. The Summary Status register indicates the following: Link Status, Full-Duplex Status, Auto-Negotiation Alert, and Speed. See Table 3. Table 3. Bits 15:4 3 2 1 0 TBR24: 10BASE-T Summary Status Register (Register 24) Description Read/Write R R R R R Name Reserved Link Status Full-Duplex Auto-Negotiation Alert Speed Default Value (hex) 0 0 0 0 0 Write as 0; Ignore on Read 1 = Link Status is up 0 = Link Status is down 1 = Operating in Full-Duplex mode 0 = Operating in Half-Duplex mode 1 = Auto-Negotiation status has changed 0 = Auto-Negotiation status unchanged 1 = Operating at 100 Mbps 0 = Operating at 10 Mbps Am79C901A 65 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . -65C to +150C Ambient Temperature (C). . . . . . . . . . -65C to +70C Ambient Temperature (I) . . . . . . . . . . -65C to +85C Supply Voltage with respect to VSS . . . . . . . . . . . . . -0.3 V to 3.63 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Temperature (TA) . . . . . . . . . . . . . . . . . .0C to +70C Supply Voltages (VDD) . . . . . . . . . . . . . 3.0 V to 3.6 V All inputs within the range: . . . . . . VSS - 0.5 V to 5.5 V Industrial (I) Devices Temperature (TA) . . . . . . . . . . . . . . . . -40C to +85C Supply Voltages (VDD) . . . . . . . . . . . . . 3.0 V to 3.6 V All inputs within the range: . . . . . . VSS - 0.5 V to 5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. 66 Am79C901A PRELIMINARY DC CHARACTERISTICS Parameter Symbol Parameter Description Digital I/O Voltage VIH Input HIGH Voltage VIH5V Input HIGH voltage (5V) VIL Input LOW Voltage VOL Test Conditions Min 2.0 2.0 Max Units V DVDD + 2.5 0.8 V V V IOL1 = 4 mA Output LOW Voltage IOL2 = 6 mA IOL3 = 12 mA IOH1 = -4 mA VOH 0.4 Output HIGH Voltage (Notes 1, 2) IOH2 = -2 mA (Note 2) 2.4 V Output Voltage on TX (peak) (Note 8) Input Differential Squelch Assert on VDIFF RX (peak) Input Differential De-Assert Voltage VDIFF on RX (peak) Digital I/O Current IOZ Output Leakage Current (Note 3) IIX Input Leakage Current (Note 4) IIL Input LOW Current (Note 5) IIH Input HIGH Current (Note 5) Power Supply Current VOUT ICC (1 Mbps) ICC (10 Mbps) ICC (Static) ICC (Idle) 1.55 300 150 1.98 520 300 V mV mV 0 V 10 10 -10 10 A A A A 1 Mbps mode on TX and RX. Outputs driving load. 10BASE-T mode on TX and RX. Outputs driving load. XCLK frequency = 0. Not transmitting. 100 mA 175 mA 45 75 mA mA Pin Capacitance CIN Pin Capacitance CCLK CLK Pin Capacitance LPIN Pin Inductance FC = 1 MHz (Note 6) FC = 1 MHz (Notes 6, 7) FC = 1 MHz (Note 6) 10 5 12 20 pF pF nH Notes: 1. VOH does not apply to open-drain output pins. 2. IOH2 applies to all other outputs. 3. IOZ applies to all output and bidirectional pins. Tests are performed at VIN = 0 V and at VDD only. 4. IIX applies to all input pins except TDI, TCLK, and TMS pins. 5. 6. 7. 8. IIL and IIH apply to the TDI, TCLK, and TMS pins. Parameter not tested. Value determined by characterization. CCLK applies only to the CLK pin. VOUT reflects output levels prior to 1: 2 transformer state. Am79C901A 67 PRELIMINARY SWITCHING WAVEFORMS Key to Switching Waveforms WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State KS000010-PAL SWITCHING TEST CIRCUITS IOL Sense Point VTHRESHOLD CL IOH 22304B-25 Figure 1. Normal and Tri-State Outputs 68 Am79C901A PRELIMINARY AC CHARACTERISTICS GPSI 10BASE-T Transmit Timing (GPSI) No. 1 2 3 4 5 6 Symbol tS tH tPD tPD tPD tPWL Parameter Description TXDAT, TXEN setup time to TXCLK edge TXDAT, TXEN hold time from TXCLK edge Transmit latency (TXEN sampled HIGH to 1st bit of data) RXCRS assert from TXEN sampled HIGH RXCRS de-assert from TXEN sampled LOW TXEN de-assertion time between packets (Note 1) Min 10 0 240 0 0 300 Max - - 360 130 130 - Unit ns ns ns ns ns ns Note: Not tested. TXCLK 6 TXEN 5 RXCRS 3 TX End of Packet 2 TXDAT, TXEN 1 Start of Packet 4 22304B-26 Figure 2. 10 Mbps Transmit Timing (GPSI) Am79C901A 69 PRELIMINARY AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (GPSI) No. 10 11 12 13 14 15 Symbol tPD tPD tPD tPD tPD tPD Parameter Description CLS assert latency from SOP RXCRS assert latency from SOP Receive latency (SOP to RXDAT valid) RXCLK edge to RXDAT transition CLS de-assert latency from EOP RXCRS de-assert latency from EOP Min 200 200 320 - 125 165 Max 300 300 430 10 250 255 Unit ns ns ns ns ns ns RXCLK RX Start of Packet 10 CLS 11 RXCRS 12 RXDAT 13 22304B-27 Figure 3. 10 Mbps Receive Start of Packet Timing (GPSI) 70 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (GPSI) (Continued) RXCLK RX End of Packet 14 CLS 15 RXCRS 22304B-28 Figure 4. 10 Mbps Receive End of Packet Timing (GPSI) 10BASE-T Transmit Clock Timing (GPSI) No. 18 19 20 Symbol tPER tPWH tPWL Parameter Description TXCLK period TXCLK pulse width HIGH TXCLK pulse width LOW Min 99.99 45 45 Max 100.01 55 55 Unit ns ns ns 10BASE-T Receive Clock Timing (GPSI) No. 18 19 20 Symbol tPER tPWH tPWL Parameter Description RXCLK period RXCLK pulse width HIGH RXCLK pulse width LOW Min 99.99 45 45 Max 100.01 55 55 Unit ns ns ns 18 19 20 TXCLK, RXCLK 22304B-29 Figure 5. 10 Mbps Transmit and Receive Clock Timing (GPSI) Am79C901A 71 PRELIMINARY AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Transmit Timing (GPSI) No. 23 24 25 26 27 28 Symbol tS tS tH tH tPD tPD Parameter Description TXDAT setup time to TXCLK TXEN setup time to TXCLK TXDAT hold time from TXCLK TXEN hold time from TXCLK Transmit Latency (TXEN sampled HIGH to SYNC pulse (5 mV)) TXEN sampled HIGH to CLS active (Note 1) Min 12 10 10 10 200 - Max - - - - 500 120 Unit ns ns ns ns ns s Note: Not tested. TXCLK 23 25 TXDAT 24 26 TXEN 27 SYNC HRTXRXP/N AID PCOM DATA 28 CLS 22304B-30 Figure 6. 1 Mbps HomePNA Transmit Timing (GPSI) 72 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Receive Timing (GPSI) No. 29 30 31 32 Symbol tPD tPD tPD tPD Parameter Description RXCLK edge to RXDAT transition (Note 1) SYNC pulse detected to RXCRS clocked as active by MAC (Note 1) Last DATA pulse crosses noise slice level to RXCRS inactive (Note 1) RXCRS inactive to CLS inactive clocked into MAC (Note 1) Min 0 650 15.98 - Max 10 850 16.10 200 Unit ns ns s ns Note: Not tested. RXCLK 29 RXDAT SYNC HRTXRXP/N AID DATA 32 31 RXCRS 30 CLS 22304B-31 DATA DATA Figure 7. 1 Mbps HomePNA Receive Timing (GPSI) Am79C901A 73 PRELIMINARY AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Clock Timing (GPSI) No. Symbol Parameter Description Clock Period Unit Idle (excluding IPG time) 35 36 37 tPER tPWH tPWL TXCLK, RXCLK period TXCLK, RXCLK pulse width HIGH TXCLK, RXCLK pulse width LOW 583.3 115.5 467.8 ns ns ns Preamble (first 64 bits of TX MAC frame) 35 36 37 tPER tPWH tPWL TXCLK, RXCLK period TXCLK, RXCLK pulse width HIGH TXCLK, RXCLK pulse width LOW 233.3 115.5 117.8 ns ns ns Data (thoughtout the data phase) 35 36 37 tPER tPWH tPWL TXCLK, RXCLK period TXCLK, RXCLK pulse width HIGH TXCLK, RXCLK pulse width LOW 233.3 ns - 10 s 115.5 117.8 ns - 10 s ns IPG (96 bit times following CRS falling edge) 35 36 37 tPER tPWH tPWL TXCLK, RXCLK period TXCLK, RXCLK pulse width HIGH TXCLK, RXCLK pulse width LOW 233.3 115.5 117.8 ns ns ns Note: During AID interval, RXCLK and TXCLK stop for up to 140 s. 35 36 37 TXCLK, RXCLK 22304B-32 Figure 8. 1 Mbps HomePNA Clock Timing (GPSI) 74 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONTINUED) MII 10BASE-T Transmit Timing (MII) No. 40 41 42 43 44 45 Symbol tS tH tPD tPD tPD tPWL Parameter Description TXD, TX_EN setup time to TXCLK edge TXD, TX_EN hold time from TXCLK edge Transmit latency (TX_EN sampled HIGH to 1st bit of data) CRS assert from TX_EN sampled HIGH CRS de-assert from TX_EN sampled LOW TX_EN de-assertion time between packets (Note 1) Min 10 0 240 0 0 1200 Max - - 360 430 430 - Unit ns ns ns ns ns ns Note: Not tested TX_CLK 45 TX_EN 44 CRS 42 TX End of Packet 41 40 TXD, TX_EN Start of Packet 43 22304B-33 Figure 9. 10 Mbps Transmit Timing (MII) Am79C901A 75 PRELIMINARY AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (MII) No. 48 49 50 51 52 53 54 Symbol tPD tPD tPD tPD tPD tPD tPD Parameter Description COL assert latency from SOP CRS assert latency from SOP Receive latency (SOP to RXD, RX_DV valid) (Note 1) RX_CLK edge to RXD, RX_DV transition RX_DV de-assert latency EOP COL de-assert latency from EOP CRS de-assert latency from EOP Min 200 200 625 - 500 100 500 Max 300 300 1275 10 900 700 900 Unit ns ns ns ns ns ns ns Note: RXD not tested. RX_CLK RX Start of Packet 48 COL 49 CRS 50 RXD, RX_DV 51 22304B-34 Figure 10. 10 Mbps Receive Start of Packet Timing (MII) 76 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (MII) (Continued) RX_CLK RX End of Packet 53 COL 54 CRS 52 RX_DV 22304B-35 Figure 11. 10 Mbps Receive End of Packet Timing (MII) Am79C901A 77 PRELIMINARY AC CHARACTERISTICS (CONTINUED) 10BASE-T Transmit Clock Timing (MII) No. 57 58 59 Symbol tPER tPWH tPWL Parameter Description TX_CLK period TX_CLK pulse width HIGH TX_CLK pulse width LOW Min 399.6 180 180 Max 400.4 220 220 Unit ns ns ns 10BASE-T Receive Clock Timing (MII) No. 57 58 59 Symbol tPER tPWH tPWL Parameter Description RX_CLK period RX_CLK pulse width HIGH RX_CLK pulse width LOW Min 399.6 180 180 Max 400.4 220 220 Unit ns ns ns 57 58 59 TX_CLK, RX_CLK 22304B-36 Figure 12. 10 Mbps Transmit and Receive Clock Timing (MII) 78 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Transmit Timing (MII) No. 62 63 64 65 Symbol tS tH tPD tPD Parameter Description TXD, TX_EN setup time to TX_CLK edge TXD, TX_EN hold time from TX_CLK edge Transmit Latency (TX_EN sampled HIGH to SYNC pulse (5 mV)) TX_EN sampled HIGH to COL active (Note 1) Min 10 10 200 - Max - - 500 120 Unit ns ns ns s Note: Not tested. TX_CLK 62 63 TXD, TX_EN TX_EN 64 SYNC HRTXRXP/N AID PCOM DATA 65 COL 22304B-37 Figure 13. 1 Mbps HomePNA Transmit Timing (MII) Am79C901A 79 PRELIMINARY AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Receive Timing (MII) No. 68 69 70 71 Symbol tPD tPD tPD tPD Parameter Description RX_CLK edge to RXD, RX_DV transitions (Note 1) SYNC pulse detected to CRS clocked as active by MAC (Note 1) Last DATA pulse crosses data slice level to CRS inactive (Note 1) CRS inactive to COL inactive clocked into MAC (Note 1) Min 0 650 15.98 - Max 10 850 16.10 200 Unit ns ns s ns Note: Not tested. RX_CLK 68 RXD, RX_DV SYNC HRTXRXP/N AID DATA 71 70 CRS 69 COL 22304B-38 DATA DATA Figure 14. 1 Mbps HomePNA Receive Timing (MII) 80 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Clock Timing (MII) No. Symbol Parameter Description Clock Period Unit Idle (excluding IPG time) 74 75 76 tPER tPWH tPWL TX_CLK, RX_CLK period TX_CLK, RX_CLK pulse width HIGH TX_CLK, RX_CLK pulse width LOW 2333.34 1165 1168 ns ns ns Preamble (first 64 bits of TX MAC frame) 74 75 76 tPER tPWH tPWL TX_CLK, RX_CLK period TX_CLK, RX_CLK pulse width HIGH TX_CLK, RX_CLK pulse width LOW 933.33 466 467 ns ns ns Data (throughout the data phase) 74 75 76 tPER tPWH tPWL TX_CLK, RX_CLK period TX_CLK, RX_CLK pulse width HIGH TX_CLK, RX_CLK pulse width LOW 933 ns - 40 s 466 ns - 40 s 467 ns - 40 s IPG (96 bit times following CRS falling edge) 74 75 76 tPER tPWH tPWL TX_CLK, RX_CLK period TX_CLK, RX_CLK pulse width HIGH TX_CLK, RX_CLK pulse width LOW 933.33 466 467 ns ns ns Note: During AID interval, RX_CLK and TX_CLK stop for up to 140 s. 74 75 76 TX_CLK, RX_CLK 22304B-39 Figure 15. 1 Mbps HomePNA Clock Timing (MII) Am79C901A 81 PRELIMINARY AC CHARACTERISTICS (CONTINUED) MDC/MDIO No. 79 80 81 82 83 84 85 Symbol tPER tPWH tPWL tPD tS tH tZ Parameter Description MDC period MDC pulse width HIGH MDC pulse width LOW MDIO output delay from MDC edge MDIO input setup time to MDC edge MDIO input hold time from MDC edge MDC to high impedance Min 400 160 160 0 8 8 5 Max - - - 300 - - 40 Unit ns ns ns ns ns ns ns 79 80 81 MDC 84 85 MDIO 83 82 22304B-40 Figure 16. MII Management Timing 82 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONTINUED) SPI No. 88 89 90 91 92 93 94 95 96 Parameter Symbol tPW tPWH tPWL tS tH tS tH tPD tPZD Parameter Name SCLK period SCLK Min pulse HIGH SCLK Min pulse LOW CS setup to SCLK CS hold to SCLK SDI setup to SCLK SDI hold to SCLK SCLK to DO valid CS to DO Hi Z Min 400 160 160 8 25 8 0 0 - Max - - - - - - - 25 50 Unit ns ns ns ns ns ns ns ns ns CS 91 SCLK 88 95 92 89 93 SDI 94 90 96 SDO 22304B-41 Figure 17. SPI Timing Am79C901A 83 PRELIMINARY AC CHARACTERISTICS (CONTINUED) 10BASE-T PMD No. 99 100 Symbol tTETD tPWKRD Parameter Description Transmit End of Transmit Data RX Pulse Width Maintain/Turn Off Threshold Test Conditions Min 250 Max 375 200 Unit ns ns |VIN| > |VTHS| (Note 1) 136 Note: RX pulses narrower than tPWDRD (min) will maintain internal Carrier Sense on. RX pulses wider than tPWKRD (max) will turn internal Carrier Sense off. 99 TX 22304B-42 Figure 18. 10 Mbps Transmit (TX) Timing Diagram 100 100 VTSQ+ RX VTSQ100 22304B-43 Figure 19. 10 Mbps Receive (RX) Timing Diagram 84 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Analog Parameter Symbol tPW tPWH tPWL tVMAXp tVMAXn No. 103 104 105 106 Parameter Name Pulse Width Pulse Width HIGH Pulse Width LOW Maximum Voltage (positive) Conditions Typical 133 67 67 Units ns ns ns V Low Power High Power Low Power High Power 1.00 2.00 1.00 2.00 107 Maximum Voltage (negative) V Notes: 1. All registers at default values and VCC = 3.3 V, 25C. 2. Measurements across HRTXTXP and HRTXTXN, differentially measured, with a 50 resistive load. 105 103 106 107 104 22304B-44 Figure 20. HomePNA PHY AC Waveform Am79C901A 85 PRELIMINARY AC CHARACTERISTICS (CONTINUED) JTAG No. 110 111 112 113 114 115 116 Parameter Symbol tPER tPWH tPWL tS tH tPD tPD Parameter Name TCK Period TCK HIGH Time TCK LOW Time TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay Min 100 45 45 8 10 3 - Max - - - - - 30 50 Unit ns ns ns ns ns ns ns Note: 1. Not tested; parameter guaranteed by design characterization. 111 112 110 TCK 113 114 TDI, TMS 115 116 TDO 22304B-45 Figure 21. JTAG (IEEE 1149.1) Test Signal Timing 86 Am79C901A PRELIMINARY AC CHARACTERISTICS (CONCLUDED) External Clock (XTAL1) No. 119 120 121 Symbol tPER tPWH tPWL Parameter Description Cycle time Cycle HIGH time Cycle LOW time Min 16.665 0.4 x TCYCLE 0.4 x TCYCLE Max 16.669 0.6 x TCYCLE 0.6 x TCYCLE Unit ns ns ns 119 120 121 XTAL1 22304B-46 Figure 22. External Clock Timing Reset Symbol tPW Parameter Description RESET to RESET Min 5000 Max - Unit ns Am79C901A 87 PRELIMINARY PHYSICAL DIMENSIONS* PL 068 Plastic Leaded Chip Carrier (measured in inches) *For reference only. BSC is an ANSI standard for Basic Space Centering. 88 Am79C901A PRELIMINARY PHYSICAL DIMENSIONS* PQT 80 Thin Plastic Quad Flat Pack (measured in millimeters) *For reference only. BSC is an ANSI standard for Basic Space Centering. Am79C901A 89 PRELIMINARY The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks Copyright 1999, 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. AlertIT, any1Home, eIMR, eIMR+, GigaPHY, HIMIB, HomePHY, IMR2, MACE, Magic Packet, NetPHY, PCnet, PCnet-Home, QuEST, and QuIET are trademarks of Advanced Micro Devices, Inc. RLL25 is a trademark of Tut Systems, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 22304C 90 Am79C901A |
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